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Publikováno v:
Microelectronics Journal. 44:321-331
Process variability are getting worse with the scaled technologies especially below 90nm, therefore for the reliable fabrication outcome, the effect of both the local and global process variability should be taken into account. In this paper, verific
Publikováno v:
Scopus-Elsevier
SBCCI
SBCCI
Due to increasing CMOS process variability, optimization for yield has become one of the crucial tasks in Integrated Circuit (IC) design especially in analog IC design. This variability is getting worse with the continuous scaling of device dimension
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http://www.scopus.com/inward/record.url?eid=2-s2.0-84870853249&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-84870853249&partnerID=MN8TOARS