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pro vyhledávání: '"Mao Xiang Yi"'
Publikováno v:
Applied Mechanics and Materials. :231-235
To reduce the test time and test cost of 3-D ICs, this paper proposed a design method of building three-dimensional scan tree, which can optimize the number of through silicon via (TSV) when limit the leaf nodes number. The proposed technique partiti
Publikováno v:
Applied Mechanics and Materials. 529:359-363
A novel concurrent core test approach is proposed to reduce the test cost of SoC. Before test, a novel test set sharing strategy is proposed to obtain a minimum size of merged test set by merging the test sets corresponding to cores under test (CUT).
Autor:
Zheng Feng Huang, Mao Xiang Yi
Publikováno v:
Applied Mechanics and Materials. :4228-4231
This paper presents a built-in SEU sensor (BISS) to detect soft errors in CMOS digital systems. BISS detects SEU-induced soft errors by monitoring the meta-stability in the flip-flops. BISS includes positive pulse generator, footed dynamic inverter a