Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Mansureh S. Moghaddam"'
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 15:1-26
Modulo-scheduled course-grain reconfigurable array (CGRA) processors excel at exploiting loop-level parallelism at a high performance per watt ratio. The frequent reconfiguration of the array, however, causes between 25% and 45% of the consumed chip
Publikováno v:
Design Automation for Embedded Systems. 21:173-194
This paper addresses the problem of mapping tasks onto an FPGA-based many-core platform where the cores typically have a limited amount of memory and thus should be frequently overlaid with a small program block that implements a task. In this regard
Autor:
Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi
Publikováno v:
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).
Publikováno v:
FPT
There has been a body of research to use stochastic computing (SC) for the implementation of neural networks, in the hope that it will reduce the area cost and energy consumption. However, no working neural network system based on stochastic computin
Autor:
Kiyoung Choi, Hyemi Min, Sukjin Kim, Mansureh S. Moghaddam, Barend Harris, Soonhoi Ha, Duseok Kang, Inpyo Bae, Euiseok Kim, Bernhard Egger, Hansu Cho
Publikováno v:
CASES
This paper presents a convolutional neural network architecture that supports transfer learning for user customization. The architecture consists of a large basic inference engine and a small augmenting engine. Initially, both engines are trained usi
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783319162133
ARC
ARC
This paper addresses an optimal mapping approach which also exploits the partial reconfiguration property of modern CGRAs. Hence this approach is not only suitable for applications which can be accommodated on the available grains but also for larger
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16ef7f8e4147cab612d3a787c23d49cd
https://doi.org/10.1007/978-3-319-16214-0_33
https://doi.org/10.1007/978-3-319-16214-0_33
Publikováno v:
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.
Publikováno v:
IPDPS Workshops
Programmable hardware built on a regular architecture can be used to address the challenges associated with using many fixed core architectures for applications which have varying compute power requirements during the lifetime of execution. The fine
Publikováno v:
DSD
Programmable hardware built on a regular architecture can partially alleviate the problem of increased defect densities associated with transistor scaling by dynamically wiring around the defects~\cite{Paul2006}. The fine granularity of FPGAs is howe