Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.

Autor: Maneatis, John G.

Publikováno v: Phase-Locking in High-Performance Systems; 2003, p396-405, 10p

Chapter 12: DESIGN OF HIGH-SPEED CMOS PLLs AND DLLs: 12.6 DLL/PLL PERFORMANCE ISSUES.

Autor: Maneatis, John George

Publikováno v: Design of High-Performance Microprocessor Circuits; 2000, p250-255, 6p

Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL.

Autor: Maneatis, John G., Jaeha Kim, McClatchie, Iain, Maxey, Jay, Shankaradas, Manjusha

Publikováno v: IEEE Journal of Solid-State Circuits; Nov2003, Vol. 38 Issue 11, p1795-1803, 9p, 4 Black and White Photographs, 12 Diagrams, 2 Charts, 2 Graphs

Chapter 12: DESIGN OF HIGH-SPEED CMOS PLLs AND DLLs: 12.2 PLL ARCHITECTURES.

Autor: Maneatis, John George

Publikováno v: Design of High-Performance Microprocessor Circuits; 2000, p236-238, 3p

Mark Horowitz's Link to Chip-to-Chip Communication: His Significant and Fundamental Contributions.

Autor: Yang, Chih-Kong Ken, Maneatis, John G.

Publikováno v: IEEE Solid-State Circuits Magazine; Jul2016, Vol. 8 Issue 3, p42-46, 5p