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A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
Autor:
Amanda Tran, Renuka Krishnamurthy, Luke Tong, Jeff Ou, Sitaraman V. Iyer, Xuguang Zhang, Kavitha Prasad, Sujatha Gowder, Doug Gambetta, Hendra Rustam, Yongping Fan, Mamatha Deshpande, John K. Wu, Ravindran Mohanavelu, Chien-chun Lin, Peter Kwok, Fulvio Spagna, Lidong Chen, Roan M. Nicholson, Marcus Pasquarella, Rohit Kumar
Publikováno v:
ISSCC
The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27154442da95010c83fb3f39bacd8a4e
https://doi.org/10.1109/isscc.2010.5433823
https://doi.org/10.1109/isscc.2010.5433823
