Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Malte Metzdorf"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37:1627-1639
Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design,
Publikováno v:
PATMOS
The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented dire
Publikováno v:
DATE
The simulation of aging related degradation mechanisms is a challenging task for timing and reliability estimations during all design phases of digital systems. Some good approaches towards accurate, efficient and applicable timing models at the regi
Publikováno v:
WESE
Modern Cyber-Physical Systems (CPS) already integrate multiple functions and this trend is expected to grow in the near future for economic reasons. Mixed-Criticality Cyber-Physical Systems (MC-CPS) impose the challenging task of integrating safety-c
Publikováno v:
ISLPED
The aging effect "Negative Bias Temperature Instability", which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durati
Autor:
Malte Metzdorf, Domenik Helms, Kim Grüttner, Frank Poppen, Wolfgang Nebel, Reef Eilers, Kai Hylla
Publikováno v:
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn).
Autor:
Max Karner, C. Kernstock, Franz Schanovsky, H. W. Karner, Zlatan Stanojevic, Reef Eilers, Malte Metzdorf, Oskar Baumgartner, Domenik Helms
Publikováno v:
2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)
We present a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell. The process involves layout-based structure generation based on technology description files, transi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7db86c69dcd4a714c4fb6f59ca5a7aba