Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Makoto Yabuuchi"'
Autor:
Yuuki Uchida, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi, Yoshio Takazawa, Mitsuhiko Igarashi, Makoto Yabuuchi
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1536-1545
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e79a94c7315a6c5d0cb4819c11ac77
https://doi.org/10.1587/transfun.2020kep0017
https://doi.org/10.1587/transfun.2020kep0017
Publikováno v:
VLSI Circuits
In the era where electromigration (EM) resistance is degraded by the continuous process advancement, we provide a solution to improve this EM resistance by 60% using our ternary content-addressable memory (TCAM). We designed the high-density TCAM mac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07d68ce0a92138b0007c7501c627c809
https://doi.org/10.1109/vlsicircuits18222.2020.9162775
https://doi.org/10.1109/vlsicircuits18222.2020.9162775
Autor:
Masao Morimoto, Yuichiro Ishii, Yoshisato Yokoyama, Makoto Yabuuchi, Shinji Tanaka, Miki Tanaka, Koji Tanaka
Publikováno v:
VLSI Circuits
A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa7bfd1120ab3af077f5094f21edf5f5
https://doi.org/10.1109/vlsicircuits18222.2020.9162985
https://doi.org/10.1109/vlsicircuits18222.2020.9162985
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:2335-2344
We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to rea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a8adebbc3c4ce0b91736c30cb1a704b
https://doi.org/10.1109/tvlsi.2018.2864267
https://doi.org/10.1109/tvlsi.2018.2864267
Publikováno v:
VLSI Circuits
A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::86582d383a6c67e41d8c44d2c2830fc8
https://doi.org/10.23919/vlsic.2019.8778187
https://doi.org/10.23919/vlsic.2019.8778187
Autor:
Koji Shibutani, Yoshio Takazawa, Mitsuhiko Igarashi, Yuuki Uchida, Yasumasa Tsukamoto, Makoto Yabuuchi
Publikováno v:
IRPS
This paper presents an analysis of impact of local bias temperature instability (BTI) by measuring Ring-Oscillators (RO) with short stage and its impact on Logic circuit and SRAM. The evaluation result of local BTI variation based on measuring RO at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::272c0d9011290b4893d8f18c1dfc6e8a
https://doi.org/10.1109/irps.2019.8720508
https://doi.org/10.1109/irps.2019.8720508
Autor:
Shunya Nagata, Tomohiro Miura, Daisuke Nakamura, Yoshisato Yokoyama, Yukari Ouchi, Yuichiro Ishii, Makoto Yabuuchi, Jiro Ishikawa, Koji Nii
Publikováno v:
A-SSCC
An effective standby power reduction of buffer/backup SRAM in MCU is proposed for power module IC (PMIC) less edge system in IoT applications. The proposed SRAM macro is implemented using 3.3 V thick-gate-oxide IO MOSs for effectively reducing the le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78bfc2a7e0916604dfcfe5e1ddd4a766
https://doi.org/10.1109/asscc.2018.8579327
https://doi.org/10.1109/asscc.2018.8579327
Autor:
Yoshiki Yamamoto, Shinji Tanaka, Hiroki Shinkawata, Yukiko Umemoto, Shiro Kamohara, Makoto Yabuuchi, Takumi Hasegawa, Kyoji Ito, Koji Nii, Yohei Sawada, Yoshihiro Shinozaki
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In 65-nm Silicon-on-Thin-Box (SOTB) technology, we demonstrate fully functional embedded 6T single-port (SP) SRAM and 8T dual-port (DP) SRAM for Smart Internet-of-Things (IoT) applications. By using back-bias (BB) control in the sleep mode, 13.72 nW/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03d35a7df99efc9cc0a2222bc20b0fbf
https://doi.org/10.1109/icsict.2018.8564844
https://doi.org/10.1109/icsict.2018.8564844
Publikováno v:
VLSI Circuits
A new 20T bitcell for dual-port (DP) ternary content addressable memory (TCAM) is proposed. To reduce the search power, we newly introduced self-adjust reference match amplifier circuit with match-line (ML) equalizing technique. Search-line (SL) over
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a11c7772af4b62ea6f6168e429ae266
https://doi.org/10.1109/vlsic.2018.8502345
https://doi.org/10.1109/vlsic.2018.8502345
Autor:
Takumi Hasegawa, Makoto Yabuuchi, Shinji Tanaka, Kyoji Ito, Koji Nii, Hiroki Shinkawata, Shiro Kamohara, Yoshiki Yamamoto, Yohei Sawada, Yoshihiro Shinozaki
Publikováno v:
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
An embedded 2-read/write (2RW) dual-port (DP) SRAM using 65-nm Silicon-on-Thin-Box (SOTB) is demonstrated. 25.85 nW/Mbit ultra-low standby power is observed by applying back-bias (BB) control in the sleep mode, reduced to 1/1000 compared to the norma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d71102fca110bb670599d7d50a56901
https://doi.org/10.1109/s3s.2017.8309224
https://doi.org/10.1109/s3s.2017.8309224