Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Makoto Saen"'
Publikováno v:
IEICE Transactions on Electronics. :382-390
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d0629ad4497572a800874f92fa45e71
https://doi.org/10.1587/transele.e100.c.382
https://doi.org/10.1587/transele.e100.c.382
Publikováno v:
IEEE Sensors Journal. 14:4026-4033
This paper presents a control method that makes it possible for a home-use manipulation system to easily grasp objects with various weights and hardnesses. To provide easy operability for nonprofessional persons, an action-intention-based man-machine
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f778c60f60d9eafc2d3a717ab782e9e0
https://doi.org/10.1109/jsen.2014.2331689
https://doi.org/10.1109/jsen.2014.2331689
Autor:
Yoshinori Kohama, Makoto Saen, Kenichi Osada, Toshihiro Hattori, Kazutaka Kasuga, Yasufumi Sugimori, Kiichi Niitsu, Naohiko Irie, Atsushi Hasegawa, Tadahiro Kuroda, Itaru Nonomura, Yasuyuki Okuma, Yasuhisa Shimazaki
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:856-862
This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9e3291f63c528be58569a66a482c420
https://doi.org/10.1109/jssc.2010.2040310
https://doi.org/10.1109/jssc.2010.2040310
Publikováno v:
IROS
A robotic-hand controller with operating performance scalable according to the number of connected tactile sensors was developed. To eliminate performance bottlenecks that appear with increasing number of sensors, the controller architecture adopts m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0316f2557d0cb1690fa43ddb53bf07f3
https://doi.org/10.1109/iros.2012.6385489
https://doi.org/10.1109/iros.2012.6385489
Publikováno v:
3DIC
In this paper, two designs of a 3D interconnection architecture for stacked processor-memory large-scale integrations (LSIs) were investigated. With consideration given to stacking formation, a hierarchical 3D interconnection architecture with a tigh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcf4ab0e0c16e4befb4265c84e4ce2ce
https://doi.org/10.1109/3dic.2010.5751440
https://doi.org/10.1109/3dic.2010.5751440
Publikováno v:
IEEE Journal of Solid-State Circuits.
A wide-range voltage-and-frequency clock synchronizer (WRCS) for maintaining synchronization during dynamic voltage-and-frequency scaling was developed. The key feature of the WRCS is short-range skew measurement based on a predictive-delay-adjustmen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1daf7bf82dff057912b844fffc46497b
https://doi.org/10.1109/jssc.2010.2065610
https://doi.org/10.1109/jssc.2010.2065610
Autor:
Shigenobu Komatsu, Atsushi Hasegawa, Itaru Nonomura, Makoto Saen, Yoshinori Kohama, Toshihiro Hattori, Kenichi Osada, Tadahiro Kuroda, Kiichi Niitsu, Yasufumi Sugimori, Kazutaka Kasuga, Naohiko Irie, Yasuhisa Shimazaki
Publikováno v:
ISSCC
This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5842634bed81d127b291e101454bec8
https://doi.org/10.1109/isscc.2009.4977517
https://doi.org/10.1109/isscc.2009.4977517
Autor:
T. Kameyama, Kenichi Osada, Naohiko Irie, Tatsuya Kamei, S. Misaka, Y. Kondoh, Takashi Ito, Yoichi Yoshida, Yusuke Nitta, Y. Tsujimoto, E. Nagahama, Makoto Saen, Tetsuya Yamada
Publikováno v:
ISSCC
A 0.4mm2 SoC resource manager controls operating frequency and allocates data bandwidth using various monitored information such as temperature, frequency of IP blocks and number of operations executed. Results show an increase of allowable temperatu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8af9db80f514a0e04f48186055929e6a
https://doi.org/10.1109/isscc.2007.373411
https://doi.org/10.1109/isscc.2007.373411
Autor:
E. Yamamoto, Hiromi Watanabe, H. Hatae, Makoto Saen, Y. Kondo, M. Hase, I. Nonomura, S. Miura, Naohiko Irie, Y. Mori, H. Ueda
Publikováno v:
CICC
We developed an elastic shared resource scheduling SoC interconnect architecture for SoCs that execute various real-time tasks in parallel. It provides both reliability for the hard real-time executions and an optimized overall performance. To meet t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78a61e53f6a68975d9623c1d847a2425
https://doi.org/10.1109/cicc.2005.1568786
https://doi.org/10.1109/cicc.2005.1568786