Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Makoto Hanawa"'
Autor:
Koji Sato, Yoshihiko Kurimoto, Yosuke Kuroda, Yutaka Makino, Suguru Kubota, Ryushi Maruyama, Makoto Hanawa, Kiyofumi Morishita, Yoshiaki Atsuta, Johji Fukada, Yasuhiro Kamikubo, Kazushige Kanki, Masakazu Kawasaki, Fumiaki Kimura, Ryuji Koshima, Katsuaki Magishi, Kenji Matsuzaki, Norifumi Otani, Masato Suzuki, Junichiro Takahashi, Takeshi Uzuka
Publikováno v:
Annals of Vascular Surgery. 69:324-331
Background The Fitzgerald classification expresses the extension of hematoma from the ruptured abdominal aortic aneurysm (rAAA) and is related to a patient's preoperative status. The objective of this study was to propose a new decision-making method
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0c01df5fc7942787990d68329ea3cdfe
https://doi.org/10.1016/j.avsg.2020.05.068
https://doi.org/10.1016/j.avsg.2020.05.068
Autor:
Yutaka Makino, Yoshihiko Kurimoto, Ryushi Maruyama, Koji Sato, Yosuke Kuroda, Makoto Hanawa, Kiyofumi Morishita, Suguru Kubota
Publikováno v:
Journal of Vascular Surgery. 65:61S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6337bcf17df254bb6dcfc81e76ef4294
https://doi.org/10.1016/j.jvs.2017.03.116
https://doi.org/10.1016/j.jvs.2017.03.116
Autor:
Ryuji, Sukegawa, Akinori, Matsumoto, Satoshi, Suzuki, Motoya, Tominaga, Kazuya, Koizumi, Yoko, Kikuchi, Kenichiro, Ozawa, Atsushi, Chiba, Masaki, Taruishi, Makoto, Hanawa, Yusuke, Saitoh
Publikováno v:
Nihon Shokakibyo Gakkai zasshi = The Japanese journal of gastro-enterology. 107(1)
A 55-year-old woman was admitted because of a tumor located in the ventral region of S4 of the liver, just beneath the diaphragm. A CT scan revealed the round tumor to be delineated as a 33 mm in size, with an outer capsule. The tumor was visualized
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=pmid________::a2b2d94cd5edd76fb8a0b64d1328338e
https://pubmed.ncbi.nlm.nih.gov/20057188
https://pubmed.ncbi.nlm.nih.gov/20057188
Autor:
Kazuo Yano, Suzuki Makoto, N. Ohki, Makoto Hanawa, Takashi Nishida, S. Shukuri, A. Kawamata, Mitsuru Hiraki, S. Morita, Koichi Seki
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:373-381
A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::078bb3836dc34872fcb91c9c90a0eaa9
https://doi.org/10.1109/4.121560
https://doi.org/10.1109/4.121560
Publikováno v:
ICCD
We have developed a superscalar RISC processor for the super technical server HITACHI SR8000. The processor includes architectural features specialized in scientific applications, in which massive amounts of data in the main memory must be processed.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::949f8c0a65dc6276d69cd5d004005117
https://doi.org/10.1109/iccd.1999.808438
https://doi.org/10.1109/iccd.1999.808438
Autor:
Makoto Hanawa, Hideo Inayoshi, Ikuya Kawasaki, Tadahiko Nishimukai, K. Takagi, T. Okada, K. Iwasaki
Publikováno v:
ICCD
A stack cache scheme in combination with a general register set is presented as an alternative to the register file. Two cache memories, a 1-K byte code cash and a four-entry cache for branch instructions, are also embedded to accelerate the pipeline
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67197f65720c1d6c5d5a91ef1c7e93db
https://doi.org/10.1109/iccd.1988.25670
https://doi.org/10.1109/iccd.1988.25670
Publikováno v:
Proceedings First Asian Test Symposium (ATS `92).
The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP proc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d7d89079faa48287110b1c95b71e6d1
https://doi.org/10.1109/ats.1992.224418
https://doi.org/10.1109/ats.1992.224418
Autor:
Shoji Shukuri, Takashi Nishida, Kazuo Yano, Tadahiko Nishimukai, Makoto Hanawa, Mitsuru Hiraki, Osamu Nishii, Suzuki Makoto
Publikováno v:
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a71f710d8a712dd777780278c03ede0a
https://doi.org/10.1109/isscc.1992.200438
https://doi.org/10.1109/isscc.1992.200438
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
A 54/spl times/54 b multiplier with 4.3 ns latency at 2.5 V supply and a 16.96 mm/sup 2/ active area is implemented in 0.3 /spl mu/m CMOS with 6.5 nm gate oxide and four-layer metal. This 4.3 ns latency multiplier is for a floating-point unit (FPU) o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75cc7cb35568900837318546764923a3
https://doi.org/10.1109/isscc.1996.488719
https://doi.org/10.1109/isscc.1996.488719
Autor:
Suzuki Makoto, Makoto Hanawa, Takashi Nishida, Mitsuru Hiraki, Osamu Nishii, Shoji Shukuri, Kazuo Yano, Tadahiko Nishimukai
Publikováno v:
ICCD
The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in par
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0042b8304b9a81a5a5a6fb17ba9749f
https://doi.org/10.1109/iccd.1991.139862
https://doi.org/10.1109/iccd.1991.139862