Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Mahyar Kargar"'
Publikováno v:
SSRN Electronic Journal.
U.S. state pensions are underfunded by trillions of dollars, but their economic burden is unclear. In a model of inefficient taxation, real estate fully reflects the cost of pension shortfalls when it is the only form of immobile capital. We study th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c312dd3d77658948e30f9dd7a5c415f5
https://doi.org/10.3386/w29405
https://doi.org/10.3386/w29405
Publikováno v:
SSRN Electronic Journal.
Autor:
Brett R. Dunn, Mahyar Kargar
Publikováno v:
SSRN Electronic Journal.
We study the relationship between funding liquidity and the valuation of mortgage-backed securities. Most of the financing for mortgage-backed securities occurs through a trade known as a dollar roll, the simultaneous sale and purchase of forward con
Publikováno v:
SSRN Electronic Journal.
Publikováno v:
SSRN Electronic Journal.
We develop an asset-pricing model with heterogeneous investors and search frictions. Trade is intermediated by risk-neutral dealers subject to capacity constraints. Risk-averse investors can direct their search towards dealers based on price and exec
Publikováno v:
SSRN Electronic Journal.
Autor:
Mahyar Kargar
Publikováno v:
SSRN Electronic Journal.
I show that the composition of the financial sector has important asset pricing implications beyond the health of the aggregate financial sector. To assess the impact of massive balance sheet adjustments within the intermediary sector during the Grea
Publikováno v:
Analog Integrated Circuits and Signal Processing. 83:271-283
A 10 Gb/s adaptive analog decision feedback equalizer with 6 taps is realized in 0.13 $$\upmu$$ μ m CMOS. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery circuit
Autor:
Siavash Fallahi, Mehdi Khanpour, Ali Nazemi, Namik Kocaman, Afshin Momtaz, Mahyar Kargar, Ullas Singh
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1875-1884
An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital qua