Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Mahmoud Reza Ahmadi"'
Autor:
Kamran Heidari, Mahmoud Reza Ahmadi, Mohammad Mehdi Forouzanfar, Behrooz Hashemi, Saeed Safari
Publikováno v:
طب اورژانس ایران, Vol 9, Iss 1 (2022)
مقدمه: ایجاد تغییرات در هر یک از بخشهای مراکز درمانی علاوه بر هزینه های مالی بسیار بالا، نیازمند هماهنگیهای قانونی و پذیرش ریسکهای
Externí odkaz:
https://doaj.org/article/03472eaccd9e47688b33d2fbbb28ab42
Autor:
Mahmoud Reza Ahmadi, Canruo Ying
Publikováno v:
IEEE Solid-State Circuits Magazine. 14:36-43
Autor:
Afshin Momtaz, Bo Zhang, Adesh Garg, Mahmoud Reza Ahmadi, Ali Nazemi, Namik Kocaman, Heng Zhang, Jun Cao, Mehdi Khanpour
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:426-439
This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A commo
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:1533-1541
This paper presents a pilot-based clock and data recovery (CDR) technique for high-speed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 55:1006-1010
This paper presents an architecture and an optimization framework that uses partial response (PR) equalization for high-speed links. PR equalization is achieved through a combined use of linear transmit equalization and decision feedback equalization
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 55:432-436
A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce
Autor:
Wei Zhang, Mahmoud Reza Ahmadi, Heng Zhang, Mohammed Abdul-Latif, Tamer Ali, Seong-Ho Lee, Guansheng Li, Afshin Momtaz, Burak Catli, Zhi Huang, Duke Tran
Publikováno v:
A-SSCC
This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of
Autor:
Siavash Fallahi, Yang Liu, Mohammed Abdul-Latif, Burak Catli, Ali Nazemi, Hassan Maarefi, Namik Kocaman, Tamer Ali, Jaehyup Kim, Mahmoud Reza Ahmadi, Afshin Momtaz
Publikováno v:
CICC
An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that o
Autor:
Bo Zhang, Namik Kocaman, Jun Cao, Ali Nazemi, Mehdi Khanpour, Afshin Momtaz, Mahmoud Reza Ahmadi, Adesh Garg, Heng Zhang
Publikováno v:
ISSCC
Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP back
Publikováno v:
CICC
This paper presents a pilot-based clock and data recovery CDR technique for high-speed serial link applications where a low-amplitude bitrate clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver us