Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Mahadeva Iyer, Natarajan"'
Publikováno v:
IEEE Electron Device Letters. 39:1011-1013
A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::539e63b830eebb23c6308a2d2e654f92
https://doi.org/10.1109/led.2018.2838760
https://doi.org/10.1109/led.2018.2838760
Publikováno v:
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).
The Semiconductor scaling from planar to recent 3D Vertical FinFET process, have seen better than expected robustness against soft errors, in addition to significant performance and area scaling. This paper presents the SER scaling trends and compari
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::342ca6d06a0c88387ff28996fc757e1c
https://doi.org/10.1109/edtm.2018.8421487
https://doi.org/10.1109/edtm.2018.8421487
Autor:
Mahadeva Iyer Natarajan, E. Ehrichs, Arfa Gondal, Rakesh Ranjan, B. Parameshwaran, Joseph Versaggi, T. Nigam, Y. Liu, Andreas Kerber
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
Reliability assessment on 2T CMOS antifuse bitcell, consisting of two core NMOSFETs having a program transistor coupled in series with a select transistor, is presented. The discrepancy in the measured time to breakdown of program transistors and pre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50ab1c2484a33a3318d0f7b4c353374c
https://doi.org/10.1109/irps.2017.7936316
https://doi.org/10.1109/irps.2017.7936316
Publikováno v:
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).
Key challenges in providing ESD protection for High Voltage CMOS technology is presented in this paper. Based on that, various methodologies to make the high voltage power transistor ESD self-protecting without changing the device IV characteristics
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c54ff1fd97aaff0e59a3965aa934e93
https://doi.org/10.1109/edtm.2017.7947533
https://doi.org/10.1109/edtm.2017.7947533
Autor:
Andreas Kerber, Mahadeva Iyer Natarajan, B. Parameshwaran, C. LaRow, T. Nigam, Rakesh Ranjan, H. Yu, Suresh Uppal
Publikováno v:
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).
The impact of source/drain e-SiGe process engineering on time dependent dielectric breakdown (TDDB) on core PFETs fabricated with bulk FinFET technology is evaluated. It is observed that thicker e-SiGe buffer layer improves the PFETs TDDB. Electrical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1015de3fa35b1db8c87395731be5b19
https://doi.org/10.1109/edtm.2017.7947492
https://doi.org/10.1109/edtm.2017.7947492
Autor:
Mahadeva Iyer Natarajan, Manjunatha Prabhu, Li Zhiqing, V. N. Vasantha Kumar, Dominic Thurmer, Jian-Hsing Lee, Tsung-Che Tsai, R.K. Jain
Publikováno v:
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition which is worse at low current compared to high ESD current. Such results cannot be re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae74dd0afc55afb8063d5d8b01e5078d
https://doi.org/10.1109/eosesd.2015.7314743
https://doi.org/10.1109/eosesd.2015.7314743
Autor:
Jagar Singh, Konstantin Korablev, Jian-Hsing Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Shesh Mani Pandey
Publikováno v:
IRPS
Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3333fdc11cb66f6ce15addbe0334d6c
https://doi.org/10.1109/irps.2015.7112721
https://doi.org/10.1109/irps.2015.7112721
Publikováno v:
IRPS
The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27b6f5e127dde884bd8ee5646fb82eac
https://doi.org/10.1109/irps.2015.7112823
https://doi.org/10.1109/irps.2015.7112823
Autor:
Premachandran, C.S, Ranjan, Rakesh, Agarwal, Rahul, Fui, Yap Sing, Paliwoda, Peter, Sarasvathi, Thangaraju, Arfa, Gondal, Patrick, Justison, Mahadeva Iyer, Natarajan
Publikováno v:
2015 IEEE 65th Electronic Components & Technology Conference (ECTC); 2015, p2144-2148, 5p