Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Madhavan Atul"'
Autor:
Rahim Kasim, Madhavan Atul, D. Kencke, J. R. Weber, G. W. Zhang, C. Perini, J. Palmer, C.-Y. Lin
Publikováno v:
2020 IEEE International Interconnect Technology Conference (IITC).
This paper focuses on the study of Co/Low-k dielectric TDDB (Time Dependent Dielectric Breakdown) in Intel’s 10nm process technology. We demonstrate that 36nm/40nm pitch Cobalt interconnects with Low-k dielectric successfully meet our technology TD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::232c91f3c0fe0e281415abfd3e8b9651
https://doi.org/10.1109/iitc47697.2020.9515670
https://doi.org/10.1109/iitc47697.2020.9515670
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76e7a8286d09b3f3bfcb1c27f6a51e61
https://doi.org/10.1109/irps45951.2020.9128345
https://doi.org/10.1109/irps45951.2020.9128345
Autor:
Kaizad Mistry, Simeon Realov, Yeoh Andrew W, Chin-Hsuan Chen, Ranjith Kumar, Ian R. Post, Ying Zhang, Tai-Hsuan Wu, Somashekar Bangalore Prakash, Madhavan Atul, Quan Shi, Xinning Wang, Peng Zheng, Gadigatla Srinivasa Chaitanya, Nabors Marni, Chris Portland Auth
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e47600e063f4c3676ee823f1726d2eed
https://doi.org/10.1109/iedm.2018.8614662
https://doi.org/10.1109/iedm.2018.8614662
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fa7cc3fb3c8d31dc8c2da50fdf17147
https://doi.org/10.1109/iitc.2018.8430489
https://doi.org/10.1109/iitc.2018.8430489
Autor:
Madhavan, Atul.
Thesis (Ph.D.)--Iowa State University, 2009.
Title from PDF title page (viewed on April 23, 2009) Includes bibliography.
Title from PDF title page (viewed on April 23, 2009) Includes bibliography.
Publikováno v:
MRS Online Proceedings Library; 2009, Vol. 1153 Issue 1, p1-6, 6p
Publikováno v:
MRS Online Proceedings Library; 2007, Vol. 989 Issue 1, p1-5, 5p
Akademický článek
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