Zobrazeno 1 - 10
of 13
pro vyhledávání: '"MH Thor"'
Publikováno v:
2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef79ec694192f12f3319015ee2848b22
https://doi.org/10.1109/ipfa55383.2022.9915715
https://doi.org/10.1109/ipfa55383.2022.9915715
Publikováno v:
2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b530dc538c08b6622cd83cdbbc80da99
https://doi.org/10.1109/ipfa53173.2021.9617404
https://doi.org/10.1109/ipfa53173.2021.9617404
Publikováno v:
2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa76e4eb6928549db8145c26b6a14f6f
https://doi.org/10.1109/ipfa53173.2021.9617424
https://doi.org/10.1109/ipfa53173.2021.9617424
Publikováno v:
Microelectronics Reliability. 92:136-142
It is well known that fail dies that exhibit obvious static power supply leakage current have a higher success of finding a defect, hence, a higher likelihood to be selected for failure analysis. When presented with choices, fail dies that exhibit si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5c145dd7b07dfe98552db5b754659db
https://doi.org/10.1016/j.microrel.2018.11.014
https://doi.org/10.1016/j.microrel.2018.11.014
Publikováno v:
2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
It is a common perception that electrical fault isolation (EFI) is the heart of a successful integrated circuit failure analysis workflow. Much effort to enhance EFI approaches is vested on improving optical resolution and system signal-to-noise in o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92504057759ae3d0828c6d74e6348a7e
https://doi.org/10.1109/ipfa49335.2020.9260742
https://doi.org/10.1109/ipfa49335.2020.9260742
Publikováno v:
2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
In this work, we optimize tester-based optical beam induced resistance change to detect defects that cannot be assessed on chip power-up and require test vectors to initialize the chip. Enhancements using a series resistor along the source path as we
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0f45e2fbf8ccd0a7cedbd320ac882cc
https://doi.org/10.1109/ipfa49335.2020.9260851
https://doi.org/10.1109/ipfa49335.2020.9260851
Publikováno v:
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA).
In this paper, we report a new dynamic laser stimulation technique based on optical beam-induced current (OBIC) variation mapping for global fault localization. A production tester exercised the chip dynamically whilst a 1064 nm wavelength laser rast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::336fab8647e373aaf16d22f4fa6f040b
https://doi.org/10.1109/ipfa47161.2019.8984836
https://doi.org/10.1109/ipfa47161.2019.8984836
Publikováno v:
Microelectronics Reliability. 119:114069
In this work, we enhance tester-based laser induced techniques to detect defects that cannot be assessed by simple chip power-up and require test cycles to initialize the chip. A statistical resistance variation mapping method is proposed and describ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a942f7ff0d21e0962f279c392fdbebfa
https://doi.org/10.1016/j.microrel.2021.114069
https://doi.org/10.1016/j.microrel.2021.114069
Publikováno v:
Microelectronics Reliability. 107:113603
In this paper, we describe the concept and applications of a dynamic laser stimulation technique based on optical beam-induced current (OBIC) variation mapping for global fault localization. A production tester exercised the chip dynamically while a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fa908ffeae41e1e6c0569d0750f6d00
https://doi.org/10.1016/j.microrel.2020.113603
https://doi.org/10.1016/j.microrel.2020.113603
Publikováno v:
International Symposium for Testing and Failure Analysis.
Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::966ddd4a9daa3e9b45e2300efe35490d
https://doi.org/10.31399/asm.cp.istfa2018p0176
https://doi.org/10.31399/asm.cp.istfa2018p0176