Zobrazeno 1 - 10
of 95
pro vyhledávání: '"M.W. Cresswell"'
Autor:
A.J. Snell, Andrew Bunting, A.W.S. Ross, Stewart Smith, A.M. Gundlach, M.W. Cresswell, A.J. Walton, R.A. Allen, B.J.R. Shulver, L.I. Haworth, J.T.M. Stevenson
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 21:495-503
Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in integrated circuit (IC) interconnect systems. The implementation of these struct
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1f0e5c19c676d7b2b9a7c32ec37a22d
https://doi.org/10.1109/tsm.2008.2004312
https://doi.org/10.1109/tsm.2008.2004312
Publikováno v:
IEEE Transactions on Engineering Management. 41:143-151
This paper describes a new procedure for using a machine-learning classification technique coupled with an expert system to increase profitability and improve throughput in a semiconductor manufacturing environment. The authors show how to use this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e29217da01141189569dba8cfa041eb
https://doi.org/10.1109/17.293381
https://doi.org/10.1109/17.293381
Autor:
B.J.R. Shulver, J.T.M. Stevenson, Stewart Smith, M.W. Cresswell, A.M. Gundlach, Camelia Dunare, A.W.S. Ross, Andrew Bunting, L.I. Haworth, A.J. Walton, R.A. Allen, A.J. Snell
Publikováno v:
2007 IEEE International Conference on Microelectronic Test Structures.
The novel overlay test structure reported in this paper was purposely designed to serve as an application-specific reference material. It features standard frame-in-frame optical overlay targets embedded in electrical test features and fabricated by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4d0c7ab8c1150459e4f722a05281996
https://doi.org/10.1109/icmts.2007.374476
https://doi.org/10.1109/icmts.2007.374476
Autor:
M.W. Cresswell, Andrew Bunting, A.J. Snell, L.I. Haworth, J.T.M. Stevenson, A.M. Gundlach, A.W.S. Ross, B.J.R. Shulver, A.J. Walton, R.A. Allen
Publikováno v:
2006 IEEE International Conference on Microelectronic Test Structures.
A novel copper damascene process is reported for fabrication of electrical critical dimension (ECD) reference material. The method of fabrication first creates an initial "silicon preform" whose linewidth is transferred into a trench using a silicon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb525eccd99c785fbb58cc3883f4d3a4
https://doi.org/10.1109/icmts.2006.1614288
https://doi.org/10.1109/icmts.2006.1614288
Publikováno v:
Proceedings of the IEEE International Conference on Microelectronic Test Structures.
This paper describes a new test structure for use in determining the thickness of a uniform conducting film. The structure incorporates the van der Pauw cross method to determine the effective sheet resistance of a vertical, uniformly doped cross sec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28ebfa6aa9cc79bb6fa1ae88869c3b66
https://doi.org/10.1109/icmts.1988.672925
https://doi.org/10.1109/icmts.1988.672925
Publikováno v:
Proceedings of the IEEE International Conference on Microelectronic Test Structures.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::507e432e893b32c869cf6fedd87e53c3
https://doi.org/10.1109/icmts.1988.672953
https://doi.org/10.1109/icmts.1988.672953
Autor:
R.A. Allen, M.W. Cresswell, C.E. Murabito, W.F. Guthrie, L.W. Linholm, C.H. Ellenwood, E. Hal Bogardus
Publikováno v:
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a696e40a10d30846029d20511a024d1e
https://doi.org/10.1109/icmts.2002.1193163
https://doi.org/10.1109/icmts.2002.1193163
Publikováno v:
Proceedings of the 1989 International Conference on Microelectronic Test Structures.
It is shown that multiple regression analysis of data from test structures designed to evaluate VLSI fabrication processes for multilevel interconnects can produce a reduced information set that can be operated on by the ID3 algorithm to produce cand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d27943d9833d01e2f6736ad0cab6f6ed
https://doi.org/10.1109/icmts.1989.39312
https://doi.org/10.1109/icmts.1989.39312
Publikováno v:
IEEE/SEMI International Symposium on Semiconductor Manufacturing Science.
The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::947ffb7ac180e58cb697d22bab50b8d7
https://doi.org/10.1109/ismss.1990.66127
https://doi.org/10.1109/ismss.1990.66127
