Zobrazeno 1 - 10
of 38
pro vyhledávání: '"M.R. Polcari"'
Autor:
B.A. Chappell, James D. Warnock, Ghavam G. Shahidi, P.A. McFarland, R.H. Dennard, M.R. Polcari, Terry I. Chappell, Bijan Davari, J.S. Neely, James H. Comfort, R.L. Franch, Tak H. Ning, C.A. Anderson
Publikováno v:
IEEE Transactions on Electron Devices. 41:2405-2412
An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05cb9369827c063e0956edeaca1e1d96
https://doi.org/10.1109/16.337456
https://doi.org/10.1109/16.337456
Autor:
K.E. Petrillo, W.H. Chang, M.R. Polcari, C.C.-H. Hsu, J.Y.-C. Sun, C.Y. Wong, M.R. Wordeman, Bijan Davari, Yuan Taur, D. Moy
Publikováno v:
IEEE Transactions on Electron Devices. 39:967-975
For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0991dc75056223bb7adb1a64be3344b
https://doi.org/10.1109/16.127490
https://doi.org/10.1109/16.127490
Autor:
C.L. Stanis, B.J. Ginsberg, U.Y.-C. Sun, J.M.C. Stork, Bernard S. Meyerson, S.R. Mader, M.R. Polcari, Joachim N. Burghartz
Publikováno v:
IEEE Transactions on Electron Devices. 38:378-385
A bipolar technology which allows for very thin base formation by ultra-high vacuum/chemical vapor deposition (UHV/CVD) epitaxy and very narrow emitter width using selective epitaxial overgrowth is presented. The key step in this selective epitaxy em
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56de6322505431633d6922afdc751793
https://doi.org/10.1109/16.69920
https://doi.org/10.1109/16.69920
Autor:
M.R. Polcari
Publikováno v:
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
The profitability and therefore the success of our semiconductor industry in the 21st century will depend on our ability to drive productivity improvements at or near historic levels. The equation is simple: as we continue to drive down cost per func
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2793100e3411f70d3eaafb8f17479401
https://doi.org/10.1109/vtsa.2007.378893
https://doi.org/10.1109/vtsa.2007.378893
Autor:
M.R. Polcari
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
The challenge of "Realizing the Roadmap" - staying on the productivity curve as outlined in the International Technology Roadmap for Semiconductors (ITRS) - has become more difficult than ever, as technology and business challenges facing the semicon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6d53b382876c4122275aa5901db3619
https://doi.org/10.1109/icicdt.2004.1309889
https://doi.org/10.1109/icicdt.2004.1309889
Autor:
M.R. Polcari, Denny D. Tang, J. Warnock, Ching-Te Chuang, Guann-Pyng Li, P.E. Biolsi, John D. Cressler, T.C. Chen, D. Danner, Tak H. Ning
Publikováno v:
Technical Digest., International Electron Devices Meeting.
The authors present a single-poly bipolar technology using an advanced transistor with an LDD (lightly doped drain)-like self-aligned lateral profile. The device is isolated by a silicon-filled deep trench with a collector-to-collector breakdown volt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e4defbb4dad44894cb32222345da98e
https://doi.org/10.1109/iedm.1988.32918
https://doi.org/10.1109/iedm.1988.32918
Autor:
M. Rodriguez, S. Brodsky, N. Mazzeo, Bijan Davari, Tak H. Ning, K. Pettrilo, R. Lombardi, T.J. Bucelot, D.S. Zicherman, P.A. McFarland, M.R. Polcari, A. Fink, Ghavam G. Shahidi
Publikováno v:
1992 Symposium on VLSI Technology Digest of Technical Papers.
It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5031f18bd6a8140812b816f32b4995e4
https://doi.org/10.1109/vlsit.1992.200671
https://doi.org/10.1109/vlsit.1992.200671
Autor:
R. Schulz, B. Wu, Keith Jenkins, D.S. Zicherman, Bijan Davari, Tak H. Ning, P.J. Coane, J.Y.-C. Sun, James D. Warnock, Denny D. Tang, Ghavam G. Shahidi, C.L. Chen, M. Rodriguez, M.R. Polcari, D. Klaus, P.A. McFarland, Yuan Taur, C.Y. Wong
Publikováno v:
1992 Symposium on VLSI Technology Digest of Technical Papers.
In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13c9b7e2694ecf1ee7d312e8a23b666b
https://doi.org/10.1109/vlsit.1992.200630
https://doi.org/10.1109/vlsit.1992.200630
Autor:
Ghavam G. Shahidi, Terry I. Chappell, M.R. Polcari, Peter W. Cook, Carl J. Anderson, B.A. Chappell, Bijan Davari, James H. Comfort, M. G. Rosenfield, Stanley E. Schuster, R.L. Franch, Tak H. Ning, Robert H. Dennard
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d10daa35367c8a8bf6b54c5880e4ddb3
https://doi.org/10.1109/iedm.1993.347275
https://doi.org/10.1109/iedm.1993.347275
Autor:
M.R. Polcari, Keith A. Jenkins, Y. T. Lii, D. Moy, J.J. Bucchignano, P.J. Coane, Shalom J. Wind, C.L. Chen, M.G.R. Thomson, David P. Klaus, M. G. Rosenfield, Y.J. Mii, Yuan Taur
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2856a22fec5bd0e54c65ab341387d8ec
https://doi.org/10.1109/iedm.1993.347383
https://doi.org/10.1109/iedm.1993.347383