Zobrazeno 1 - 10
of 21
pro vyhledávání: '"M.R. Dwarakanath"'
Autor:
J. Junkkari, R.S. Shariatcloust, G.A. Wilson, L. Siren, D.W. Green, T. Ali-Vehmas, H. Khorramabadi, J.G. Ruch, M.R. Dwarakanath, K-H. Lau, K. Nagaraj, O.E. Agazzi, K.R. Lakshmikumar, J.R. Barner, J. Kumar
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1951-1958
The authors describe the design of a baseband codec for European and North American digital cellular telephone applications. By integrating all the data conversion circuitry, this chip offers a low-cost, low-power solution to baseband signal processi
Autor:
O.E. Agazzi, C.M. Gerveshi, M.L. Heiskanen, R.B. Blake, T.R. Peterson, P.H. Tracy, M.R. Dwarakanath, R.F. Shaw, W.R. McDonald, V. Friedman, R.W. Walden, J. Kumar, D.L. Price, G.A. Wilson, J. Anidjar, H. Khorramabadi, N.L. Gottfried, J.M. Khoury, Nallepilli S. Ramesh
Publikováno v:
Proceedings of the IEEE Custom Integrated Circuits Conference.
Architectural and circuit innovations resulting in a 260mW single-chip ISDN U-interface transceiver wii h a range of more than 21Kft of AWG26 cable are described. These include a new scheme for jitter compensation using a two-phase decimator that res
Autor:
T. Koh, N.L. Gottfried, G.A. Wilson, R.B. Blake, J. Kumar, C.M. Gervershi, R. Crochiere, W.R. McDonald, M.R. Dwarakanath, O.E. Agazzi, R.A. Wilson, D.R. Cassiday, S.S. Haider, T.M. Lalumia, R.W. Walden, R.F. Shaw, Nallepilli S. Ramesh, M.L. Heisakanen
Publikováno v:
ICASSP
The authors discuss major issues related to algorithms and architecture of the transceiver system and be the signal processor that they designed and implemented in a single VLSI chip. The functions of each block are described in the context of the ov
Autor:
M.R. Dwarakanath, P.H. Tracy, K.M. Tham, R. Ramachandran, K.R. Lakshmikumar, A.R. Mastrocola, D.E. Sherry, J. Anidjar, G.T. Brauns, S.A. Werner
Publikováno v:
1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
This paper describes the low-power techniques used to design the Clock/Data recovery, Jitter Filter and the high current Line Driver circuits in a Quad Line Interface for DS1/CEPT applications.
Autor:
K.R. Lakshmikumar, D.W. Green, K. Nagaraj, K-H. Lau, O.E. Agazzi, J.R. Barner, H. Khorramabadi, R.S. Shariatcloust, G.A. Wilson, M.R. Dwarakanath, J.G. Ruch, J. Kumar, T. Ali-Vehmas, J. Junkkari, L. Siren
Publikováno v:
1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Publikováno v:
IEEE Journal of Solid-State Circuits. 16:308-315
A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission
Publikováno v:
Nuclear Physics A. 315:253-268
The cross section for the 11 B(p, 3α) reaction has been measured for lab bombarding energies from 35.4 keV to 1500 keV. The astrophysical S -factor is calculated for this range of energies and an empirical fit to S is presented. The reaction rate
Publikováno v:
Nuclear Physics A. 233:286-296
The partial widths of the second T = 1 state of 12 C, at 16.11 MeV excitation energy, have been determined by measuring the 11 B(p, γ) and 11 B(p, α) cross sections at the E p = 163 keV resonance corresponding to this state. These measurements resu
Publikováno v:
Nuclear Physics A. 128:325-332
Absolute cross sections for the 3He(α, γ)7Be reaction were determined for c.m. energies between 164 and 245 keV. The results are in good agreement with previous values obtained by Parker and Kavanagh, where the experiments overlap. The energy regio
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