Zobrazeno 1 - 5
of 5
pro vyhledávání: '"M.M.R. Gala"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14:1388-1398
Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6583fb92c442ce5db0c9d00f0f970de8
https://doi.org/10.1109/43.469664
https://doi.org/10.1109/43.469664
Publikováno v:
VTS
Testing of one dimensional unilateral iterative logic arrays (ILAs) of combinational cells under multiple faults is discussed. It has been shown that it is possible to generate a test set for ILAs with primary outputs under multiple faults. Some ILAs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ad3742a89b9a94a34e9f48fd85c3285
https://doi.org/10.1109/vtest.1993.313327
https://doi.org/10.1109/vtest.1993.313327
Publikováno v:
VTS
A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One appl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acc5a778ac125e81a784c03fede388f0
https://doi.org/10.1109/vtest.1993.313323
https://doi.org/10.1109/vtest.1993.313323
Publikováno v:
VTS
Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8289abf8aeda824015305695052ffa58
https://doi.org/10.1109/vtest.1994.292293
https://doi.org/10.1109/vtest.1994.292293
Autor:
Y.-Y.J. Leung, M.M.R. Gala
Publikováno v:
Proceedings of the 33rd Midwest Symposium on Circuits and Systems.
A VLSI algorithm was developed for the computation of the remainder of A*B mod N based on radix-4 arithmetic. The speed of the computation is enhanced by using radix-4 multiplication and radix-4 SRT division. The hardware design which is suitable for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f2d4d8ee811ba74aa8e8c6ed8e72a19
https://doi.org/10.1109/mwscas.1990.140735
https://doi.org/10.1109/mwscas.1990.140735