Zobrazeno 1 - 10
of 35
pro vyhledávání: '"M.J. Helix"'
A new technique to determine the average low-field electron mobility in MESFET using C-V measurement
Publikováno v:
IEEE Transactions on Electron Devices. 39:1982-1986
A method to determine the average low-field mobility using the number of electrons available for the conduction based on C-V measurement is proposed. This technique requires neither information of the doping profile in the channel, nor the exact valu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7216999294a1fe5f03f5fbbb3292aed
https://doi.org/10.1109/16.155868
https://doi.org/10.1109/16.155868
Autor:
B.-J. Moon, M.J. Helix
Publikováno v:
IEEE Transactions on Electron Devices. 40:32-34
A method for extracting the effective channel thickness of MESFETs fabricated in fully ion-implanted processes is proposed. This method is based on the measurement of the transconductance parameter beta . Since the expression for beta includes the ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e30604112cc543f1c141bf0a8310f743
https://doi.org/10.1109/16.249420
https://doi.org/10.1109/16.249420
Publikováno v:
IEEE Journal of Solid-State Circuits. 17:1226-1231
Analyses the fan-out capability and speed of a Schottky diode-FET logic (SDFL) gate in the context of an analytical model which links the fan-out to the parameters of the pull-up, pull-down, and switching transistors, and to the supply voltages. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b43950d05a4fa0fad210eabc35f610bc
https://doi.org/10.1109/jssc.1982.1051886
https://doi.org/10.1109/jssc.1982.1051886
Publikováno v:
Thin Solid Films. 55:143-148
A versatile r.f. plasma deposition system used to deposit high quality Si3N4 films at low temperature (200–350°C) is described. By introducing the reactant gases separately and reactively reducing the oxygen content of the system, films which exhi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2df19deccb01339e52294c1034914ddb
https://doi.org/10.1016/0040-6090(78)90082-2
https://doi.org/10.1016/0040-6090(78)90082-2
Autor:
G. Y. Lee, K.W. Lee, S.A. Hanka, C.A. Arsenault, Barry K. Gilbert, Andrzej Peczalski, Michael Shur, M.J. Helix, S.A. Jamison, W.R. Betten, S.M. Karwoski, Roderick D. Nelson, P.C.T. Roberts, Tho T. Vu, S.K. Swanson, G.M. Lee, P.J. Vold, B.A. Naused
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:224-238
Using GaAs self-aligned gate MESFETs, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5554bdd2e1e61dd1cd30234aea0471e
https://doi.org/10.1109/4.283
https://doi.org/10.1109/4.283
Publikováno v:
IEEE Transactions on Electron Devices. 32:987-992
Techniques which allow us to determine the series source, drain, and gate resistances and the electron saturation velocity of ion-implanted GaAs FET's are described. These techniques are based on the "end" resistance measurements. The theory of this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77329010183ba44559ba0b9d9aef94c6
https://doi.org/10.1109/t-ed.1985.22058
https://doi.org/10.1109/t-ed.1985.22058
Publikováno v:
Journal of The Electrochemical Society. 124:1781-1784
Low temperature photoluminescence and Auger electron spectroscopy have been used to study chemical-vapor deposited SiO2 and SigN4 layers as en- capsulants for high temperature annealing of GaAs. Silicon dioxide or silicon oxynitride layers allow out-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3cd4582d02ab95f7c76c6cceafb518e
https://doi.org/10.1149/1.2133156
https://doi.org/10.1149/1.2133156
Publikováno v:
Journal of Applied Physics. 48:3342-3346
Differential resistivity and Hall‐effect measurements have been utilized to study the annealing behavior and electrical carrier‐distribution profiles of Be‐implanted GaAs. A maximum of 90–100% electrical activation occurs during 900 °C annea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1875d0c092529312a97663111ddebf72
https://doi.org/10.1063/1.324218
https://doi.org/10.1063/1.324218
Publikováno v:
IEEE Journal of Solid-State Circuits. 13:426-429
The fabrication and characteristics of planar junctions in GaAs formed by Be ion implantation are discussed. The critical processing step is shown to be the use of a carefully deposited oxygen-free Si/SUB 3/N/SUB 4/ encapsulation during post-implanta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cfe96f6d1807acb38c76b88defd9a39
https://doi.org/10.1109/jssc.1978.1051072
https://doi.org/10.1109/jssc.1978.1051072
Autor:
K. V. Vaidyanathan, C. A. Jun. Evans, D. J. Wolford, B. G. Streetman, R. J. Blattner, M.J. Helix
Publikováno v:
Chemischer Informationsdienst. 9
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f26b86d28d309139a27f4ee593c4b72
https://doi.org/10.1002/chin.197814011
https://doi.org/10.1002/chin.197814011