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Publikováno v:
IEEE Transactions on Aerospace and Electronic Systems. 37:280-285
A parallel two-stage acquisition technique is described for direct sequence spread spectrum (DS/SS) range finding applications. The technique offers hardware complexity that scales better with code length than matched filter correlators while providi
Autor:
Wm Wulf, M.H. Salinas, Robert H. Klenke, Dee A. B. Weikle, Sally A. McKee, James H. Aylor, S.I. Hong
Publikováno v:
IEEE Transactions on Computers. 49:1255-1271
Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal loca
Publikováno v:
Computer Music Journal. 23:33-47
33 Computer Music Journal, 23:4, pp. 33–47, Winter 1999 © 1999 Massachusetts Institute of Technology. Physical modeling of musical instruments has proven to be an interesting and useful technique for sound synthesis, because it provides the variab
Autor:
M.H. Salinas, James H. Aylor, Kenneth L. Wright, Robert H. Klenke, Sally A. McKee, Wm Wulf, A.P. Batson
Publikováno v:
Computer. 31:54-63
Processor speeds are increasing so much faster than memory speeds that within a decade processors may spend most of their time waiting for data. Most modern DRAM components support modes that make it possible to perform some access sequences more qui
Publikováno v:
IEEE Design & Test of Computers. 10:42-54
A methodology using a VHDL (VHSIC hardware description language) to create executable models of computer architectures independent of implementation attributes is described. The authors present such a model of a processor architecture known as the WM
Publikováno v:
Annual Reliability and Maintainability Symposium, 2003..
In train and transit applications, the occurrence of a single hazard (fault) may be quite catastrophic resulting in significant societal costs, ranging from loss of life to major asset damages. The axiomatic safety-critical assessment process (ASCAP)
Publikováno v:
ICCD
A novel methodology is presented which allows the creation of implementation-independent functional models of systems. The methodology uses the VHSIC (very high speed integrated circuit) hardware description language (VHDL) which leads to the possibi
Publikováno v:
Proceedings of Eighth International Application Specific Integrated Circuits Conference.
This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in
Publikováno v:
HPCA
Processor speeds are increasing rapidly and memory speeds are not keeping up. Streaming computations (such as multimedia or scientific applications) are among those whose performance is most limited by the memory bottleneck. Rambus hopes to bridge th