Zobrazeno 1 - 10
of 30
pro vyhledávání: '"M.E. Nier"'
Publikováno v:
Microelectronic Engineering. :859-865
The current challenges of developing an etching process for the patterning of MOSFET gates with critical dimensions below 30 nm has been tackled by various independent R&D groups world-wide. This paper discusses the commonly encountered problems for
A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket
Autor:
Christian Caillat, P. Mur, M. Heitzmann, B. Dal’zotto, M.E. Nier, Simon Deleonibus, S. Tedesco, G. Guegan
Publikováno v:
Solid-State Electronics. 46:343-348
Designs of 0.10 μm buried p-channel devices have been studied and compared. We demonstrate that silicon p-MOSFETs with n-type polysilicon gate could achieve a good control of short channel effects. Based on new channel design optimisation using thro
Autor:
G. Lecarval, J.L. Dichiaro, M. Heitzmann, A.M. Papon, P. Mur, F. Jourdan, Christian Caillat, F. Allain, François Martin, M.E. Nier, P. Fugier, B. Dal’zotto, Simon Deleonibus, Alain Toffoli, G. Guegan, Bernard Previtali, S. Tedesco, S. Biswas
Publikováno v:
Solid-State Electronics. 46:349-352
Autor:
H. Achard, L. Ulmer, F. Ducroquet, M.E. Nier, S. Tedesco, F. Coudert, T. Farjot, J.-F. Lugand, M. Heitzmann, Simon Deleonibus, Y. Gobil, Bernard Previtali
Publikováno v:
IEEE Transactions on Electron Devices. 48:1816-1821
Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved fo
Autor:
Denis Mariolle, P. Mur, T. Charvolin, M. Heitzman, L. Palun, D. Fraboulet, François Martin, B. Dal'Zotto, F. Tardif, S. Tedesco, M.E. Nier
Publikováno v:
Microelectronic Engineering. 53:167-170
This paper describes the successive fabrication steps on 8'' wafers of a silicon Single Electron Transistor (SET) using hybrid (e-beam/DUV) lithography. This process is compatible with Silicon On Insulator MOSFET technology, and opens a way to fabric
Autor:
M. Heitzmann, M.E. Nier
Publikováno v:
Microelectronic Engineering. 53:159-162
The evaluation of electrical performances of ultimate MOSFET requires lithography and etching of poly gate in the 30 nm range while gate oxide thickness is close to 1.2 nm. This paper describes the process developed for etching of these ultra narrow
Autor:
Christian Caillat, S. Biswas, G. Lecarval, B. Dal'zotto, G. Guegan, P. Mur, D. Souil, M.E. Nier, M. Heitzmann, François Martin, Simon Deleonibus, A.M. Papon, S. Tedesco
Publikováno v:
IEEE Electron Device Letters. 21:173-175
We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N/sup -/ arsenic implanted extensions and BF/sub 2/ pockets. The devi
Autor:
Emmanuel Hadji, C. Seassal, M. Heitzmann, Xavier Letartre, Emmanuel Picard, B. Dal’zotto, T. Charvolin, M.E. Nier, Marc Zelsmann, Pedro Rojo-Romeo
Publikováno v:
Journal of Applied Physics
Journal of Applied Physics, American Institute of Physics, 2004, vol. 95, p. 1606
Journal of Applied Physics, 2004, vol. 95, p. 1606
Journal of Applied Physics, American Institute of Physics, 2004, vol. 95, p. 1606
Journal of Applied Physics, 2004, vol. 95, p. 1606
Optical properties of a straight 50-row-long photonic crystal waveguide (PCW) are reported. This waveguide is obtained by removing one row of air holes in a triangular lattice two-dimensional photonic crystal etched on a silicon-on-insulator substrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d683cab60873f9f1c59dbb53cf89acf4
https://hal.archives-ouvertes.fr/hal-00390521
https://hal.archives-ouvertes.fr/hal-00390521
Autor:
C. Le Royer, Xavier Jehl, Simon Deleonibus, P. Scheiblin, M. Sanquer, Alain Toffoli, G. Molas, M.E. Nier, D. Fraboulet, Denis Mariolle, G. Le Carval, D. Deleroyelle, B. De Salvo, L. Mollard, P. Rivallin
Publikováno v:
32nd European Solid-State Device Research Conference.
Deca-nanometer size SOI devices have been fabricated with a conventional SOI-MOSFET process adapted in order to favor Coulomb blockade in a silicon channel locally constricted. The device is designed in a thin highly doped SOI layer. At low temperatu
Autor:
Xavier Letartre, Pedro Rojo-Romeo, S. Tedesco, T. Charvolin, Emmanuel Picard, M.E. Nier, M. Assous, B. Dal’zotto, M. Zelsman, Emmanuel Hadji, Christian Seassal
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2002, vol. 61, p. 545
Microelectronic Engineering, 2002, vol. 61, p. 545
Microelectronic Engineering, Elsevier, 2002, vol. 61, p. 545
Microelectronic Engineering, 2002, vol. 61, p. 545
We present results on the fabrication of optical devices based on photonic crystals on silicon-on insulator substrates. Guides, microcavities, add-drop filters have been obtained with process compatible with CMOS technologies.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b205993e08f5aad20c5b4666578d29bf
https://hal.archives-ouvertes.fr/hal-00390519
https://hal.archives-ouvertes.fr/hal-00390519