Zobrazeno 1 - 10
of 22
pro vyhledávání: '"M.-A. Jaud"'
Autor:
M. -A. Jaud, W. Vandendaele, B. Rrustemi, A. G. Viey, S. Martin, C. Le Royer, L. Vauche, S. Martinie, R. Gwoziecki, R. Modica, F. Iucolano, T. Poiroux
Publikováno v:
IEEE Transactions on Electron Devices. 69:669-674
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2f7c760d90e820c1a34e49ba5a86508
https://doi.org/10.1109/ted.2021.3136150
https://doi.org/10.1109/ted.2021.3136150
Publikováno v:
Solid-State Electronics. 201:108594
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a2ad38b3024604391b0677d297bc246
https://doi.org/10.1016/j.sse.2023.108594
https://doi.org/10.1016/j.sse.2023.108594
Autor:
W. Vandendaele, M.-A. Jaud, A. G. Viey, B. Mohamad, C. Le Royer, L. Vauche, A. Constant, R. Modica, F. Iucolano, R. Gwoziecki
Publikováno v:
2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66ee6e914fcd7a8351df2159924e7adf
https://doi.org/10.1109/ispsd49238.2022.9813613
https://doi.org/10.1109/ispsd49238.2022.9813613
Autor:
C. Le Royer, B. Mohamad, J. Biscarrat, L. Vauche, R. Escoffier, J. Buckley, S. Becu, R. Riat, C. Gillot, M. Charles, S. Ruel, P. Pimenta-Barros, N. Posseme, P. Besson, F. Boudaa, C. Vannuffel, W. Vandendaele, A.G. Viey, A. Krakovinsky, M.-A. Jaud, R. Modica, F. Iucolano, R. Le Tiec, S. Levi, M. Orsatelli, R. Gwoziecki, V. Sousa
Publikováno v:
2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44dbbb3d01be89be8061e02121c4b306
https://doi.org/10.1109/ispsd49238.2022.9813672
https://doi.org/10.1109/ispsd49238.2022.9813672
Autor:
B. Rrustemi, A. G. Viey, M.-A. Jaud, F. Triozon, W. Vandendaele, C. Leroux, J. Cluzel, S. Martin, C. Le Royer, R. Gwoziecki, R. Modica, F. Iucolano, F. Gaillard, T. Poiroux, G. Ghibaudo
Publikováno v:
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5af867dcfe69bddd8c164de72a7ca7a8
https://doi.org/10.1109/essderc53440.2021.9631766
https://doi.org/10.1109/essderc53440.2021.9631766
Autor:
B. Rrustemi, C. Piotrowicz, M-A. Jaud, F. Triozon, W. Vandendaele, B. Mohamad, R. Gwoziecki, G. Ghibaudo
Publikováno v:
Solid-State Electronics. 194:108356
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1bdfcbab6dbcd9a13016c9d79f2c87ef
https://doi.org/10.1016/j.sse.2022.108356
https://doi.org/10.1016/j.sse.2022.108356
Publikováno v:
IEEE Transactions on Electron Devices. 63:781-786
In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3f505c18ac5011ba963e3e7597aaa6d
https://doi.org/10.1109/ted.2015.2506781
https://doi.org/10.1109/ted.2015.2506781
Autor:
Michel Haond, Maud Vinet, Alain Aurand, V. Farys, E. Baylac, A. Claverie, E. Petitprez, Emmanuel Josse, Raphael Bingert, M-A. Jaud, T. Poiroux, E. Bechet, Jean-Claude Marin, Didier Dutartre, S. Delmedico, Olivier Weber, C. Bernicot, E. Bernard, P. Sardin, F Andrieu, S. Ortolland, Joris Lacord, E. Serret, R. Berthelon, Patrick Scheer, A. Pofelski, Pierre Perreau, Denis Rideau
Publikováno v:
VLSI Technology, 2016 IEEE Symposium on
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573425⟩
2016 IEEE Symposium on VLSI Technology
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573425⟩
2016 IEEE Symposium on VLSI Technology
cited By 4; International audience; We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bb1321d14ae9eb2e1bfa303be111c6af
https://doi.org/10.1109/vlsit.2016.7573425
https://doi.org/10.1109/vlsit.2016.7573425
Publikováno v:
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).
The optimization of Reconfigurable FET (RFET) devices is carried out in planar SOI technology. The electrostatic behavior, drive current and logic inverter operation are then discussed and compared with planar 28nm FDSOI devices.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcfbac70ce49edf7531328012e433d18
https://doi.org/10.1109/ulis.2016.7440038
https://doi.org/10.1109/ulis.2016.7440038
Autor:
Amara Amara, M. Vinet, F. Andrieu, Olivier Weber, M.-A. Jaud, Frederic Boeuf, O. Rozeau, O. Faynot, Olivier Thomas, Thierry Poiroux, J-P Noel, C. Fenouillet-Beranger, P. Rivallin, P. Scheiblin
Publikováno v:
IEEE Transactions on Electron Devices. 58:2473-2482
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology optio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79d705643cdb970225518bd6fe3d419c
https://doi.org/10.1109/ted.2011.2155658
https://doi.org/10.1109/ted.2011.2155658