Zobrazeno 1 - 5
of 5
pro vyhledávání: '"M. Y. Kamkar"'
Autor:
Patrick Truitt, Christopher Raum, Adrian T. Lee, M. Y. Kamkar, Daniel Yohannes, Benjamin Westbrook, Trevor Sasse, Aritoki Suzuki
Publikováno v:
IEEE Transactions on Applied Superconductivity. 29:1-4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::378f4007e3078921d945ebca0dbdc647
https://doi.org/10.1109/tasc.2019.2905737
https://doi.org/10.1109/tasc.2019.2905737
Autor:
Oleg A. Mukhanov, Igor V. Vernik, Anubhav Sahu, M. Y. Kamkar, C. Shawawreh, Alex F. Kirichenko, Denis Amparo, A. Inamdar, M. Miller, Jie Ren
Publikováno v:
IEEE Transactions on Applied Superconductivity. 27:1-6
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeof
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81f1f3bbe531a2d1c233b2d9c1bf1ade
https://doi.org/10.1109/tasc.2017.2669581
https://doi.org/10.1109/tasc.2017.2669581
Autor:
Lucian Remus Albu, Maximilian Miller, M. Y. Kamkar, Oleg A. Mukhanov, Igor V. Vernik, Jason Walter, Alex F. Kirichenko
We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1bfe95e91c08ac38afc748f5c29e0a2
http://arxiv.org/abs/1902.09500
http://arxiv.org/abs/1902.09500
We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bi-directional SHIFT instruction of an 8-bit argument. It
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bd3c69a7a1c552de38d2cf932bc06ab7
Autor:
T.V. Filippov, M. Y. Kamkar, Jason Walter, Igor V. Vernik, O.A. Mukhanov, Denis Amparo, Alex F. Kirichenko
Publikováno v:
2017 16th International Superconductive Electronics Conference (ISEC).
We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f7e64e0e10c81d305eb10ce65fcd872
https://doi.org/10.1109/isec.2017.8314191
https://doi.org/10.1109/isec.2017.8314191