Zobrazeno 1 - 1
of 1
pro vyhledávání: '"M. Wagih Ismai"'
Publikováno v:
IEEE Solid-State Circuits Letters. 3:366-369
A novel ADC architecture is introduced with a sampling rate comparable to flash converters, but with reduced power consumption. Broadband active delay circuits pass the input along with a clock through a continuous-time pipeline. Efficient internal b