Zobrazeno 1 - 10
of 125
pro vyhledávání: '"M. Toledano Luque"'
Autor:
M. Toledano-Luque, B. Zhu, B. Min, T. Nigam, P. Srinivasan, P. Paliwoda, S. Cimino, Z. Chbili, M. Iqbal Mahmud, A. Gupta, T. Shen, T. Kauerauf
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
The endless demand for high performance and low power CMOS devices at extremely scaled cell dimensions led the semiconductor industry to migrate to FinFET structures. This evolution has brought higher integration complexity and has forced the reliabi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0a6f5a0299168bfd30c0e08ab0b1f42
https://doi.org/10.1109/edtm.2019.8731235
https://doi.org/10.1109/edtm.2019.8731235
Autor:
M. Toledano-Luque, Franz Schanovsky, Ben Kaczer, Oskar Baumgartner, Markus Bina, Wolfgang Goes, Tibor Grasser
Publikováno v:
ECS Transactions. 58:31-47
Recently, correlated drain and gate current fluctuations have been observed in nano-scaled MOSFETs, indicating that their occurrence is linked to the same defect. One explanation for this observation can be given by the multi-state defect model, whic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc681d8be42ed39462f9cefb34d6d68a
https://doi.org/10.1149/05807.0031ecst
https://doi.org/10.1149/05807.0031ecst
Autor:
Marc Heyns, Guido Groeseneken, Lars-Ake Ragnarsson, Philippe Roussel, Andriy Hikavyy, Jacopo Franco, T. Kauerauf, Liesbeth Witters, M. Toledano-Luque, Jerome Mitard, Naoto Horiguchi, Geert Hellings, Tibor Grasser, Geert Eneman, Moonju Cho, Ben Kaczer
Publikováno v:
ECS Transactions. 50:177-195
We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a sign
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e334c8a89876db880f8e4f4b1b6bdd7b
https://doi.org/10.1149/05009.0177ecst
https://doi.org/10.1149/05009.0177ecst
Autor:
B. Kaczer, C. Chen, P. Weckx, Ph. J. Roussel, M. Toledano-Luque, J. Franco, M. Cho, J. Watt, K. Chanda, G. Groeseneken, T. Grasser
Publikováno v:
2014 IEEE International Reliability Physics Symposium.
We consider in detail the aspects of maximizing application performance while maintaining its sufficient reliability on the specific case of serially connected nFETs. Serially connected nFETs used in some digital CMOS applications, such as SRAM decod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa77f9fb7bbd95eb941bace7cc126d86
https://doi.org/10.1109/irps.2014.6860596
https://doi.org/10.1109/irps.2014.6860596
Autor:
Aaron Thean, K. Han, A. De Keersgieter, Anup Phatak, Bertrand Parvais, H. Dekkers, Adam Brand, S. A. Chew, Katia Devriendt, Tom Schram, L.-A. Ragnarsson, Naoto Horiguchi, Naomi Yoshida, Benjamin Colombeau, M. Toledano Luque, A. Van Ammel
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19b2d1ce62d6d0375f2135011268ce1a
https://doi.org/10.1109/vlsit.2014.6894359
https://doi.org/10.1109/vlsit.2014.6894359
Autor:
Tibor Grasser, B. Kaczer, Kaushik Chanda, Guido Groeseneken, J. T. Watt, Christopher Chen, M. Toledano Luque, Pieter Weckx
Publikováno v:
2013 IEEE International Integrated Reliability Workshop Final Report.
The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and worklo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220b6335ba88e8898572858f66b5e677
https://doi.org/10.1109/iirw.2013.6804167
https://doi.org/10.1109/iirw.2013.6804167
Publikováno v:
Bias Temperature Instability for Devices and Circuits ISBN: 9781461479086
The statistics of bias temperature instability (BTI) is derived within the “defect-centric” paradigm of device degradation. This paradigm is first briefly reviewed, drawing on similarities between BTI and random telegraph noise (RTN). The impact
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e03cdf7549272cfc6078fa1ea5a86a9
https://doi.org/10.1007/978-1-4614-7909-3_7
https://doi.org/10.1007/978-1-4614-7909-3_7
Autor:
M. Toledano-Luque, B. Kaczer
Publikováno v:
Bias Temperature Instability for Devices and Circuits ISBN: 9781461479086
As the result of the vertical scaling of the CMOS technology, high-κ materials were introduced in the gate stack in order to reduce leakage current while keeping electrostatic control over the channel. Despite the high level of the bulk defects of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e7e9b17d167fd2833dd299fec85dfb1
https://doi.org/10.1007/978-1-4614-7909-3_23
https://doi.org/10.1007/978-1-4614-7909-3_23
Autor:
M. Toledano Luque, Guido Groeseneken, Tibor Grasser, J. Franco, B. Kaczer, Pieter Weckx, Ph. J. Roussel
Publikováno v:
2012 International Conference on Emerging Electronics.
In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is stochastic,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3cc4909cb17304ed111009a0fe1120e1
https://doi.org/10.1109/icemelec.2012.6636222
https://doi.org/10.1109/icemelec.2012.6636222
Autor:
Ben Kaczer, J. Van Houdt, Pieter Weckx, Ph. J. Roussel, Gouri Sankar Kar, Robin Degraeve, Guido Groeseneken, Baojun Tang, Jacopo Franco, A. Suhane, M. Toledano-Luque, G. Van den bosch, Antonio Arreghini
Publikováno v:
2012 International Electron Devices Meeting.
3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10nm nonvolatile memory technology node and beyond (1–2) provided that a significant drive current I READ is delivered at a fixed reading gate voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21431965ec4c0191941d3be1d1b7304a
https://doi.org/10.1109/iedm.2012.6479009
https://doi.org/10.1109/iedm.2012.6479009