Zobrazeno 1 - 10
of 146
pro vyhledávání: '"M. Nowick"'
Autor:
M. Nowicki, A. Wierzbowska, E. Stec-Martyna, D. Kulczycka-Wojdala, G. Nowicki, A. Szmigielska-Kapłon
Publikováno v:
HemaSphere, Vol 6, Pp 1837-1838 (2022)
Externí odkaz:
https://doaj.org/article/cf2a710d9d0440859a575e26bbd66dc1
Autor:
Steven M. Nowick, Kshitij Bhardwaj, Alberto Ghiribaldi, Davide Bertozzi, Weiwei Jiang, Greg Sadowski, Wayne Burleson, Gabriele Miorandi
Publikováno v:
IEEE Micro. 41:69-81
In this article, a novel interconnect technology is presented for the cost-effective and flexible design of asynchronous networks-on-chip. It delivers asynchrony in heterogeneous system integration while yielding low-energy on-chip data movement. The
Publikováno v:
2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).
Autor:
Kshitij Bhardwaj, Steven M. Nowick
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:350-363
Multicast communication (one-to-many) is common in parallel architectures and emerging areas, such as neuromorphic computing. However, there is very limited research in supporting multicast in asynchronous networks-on-chip (NoCs). This paper proposes
Autor:
Maria Kurchuk, Bob Schell, Sharvil Patil, Yannis Tsividis, Steven M. Nowick, Christos Vezyrtzis, Pablo Martinez-Nuevo
Publikováno v:
Event-Based Control and Signal Processing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e04d77e0630a30b5aca12f9b25bf365
https://doi.org/10.1201/b19013-15
https://doi.org/10.1201/b19013-15
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2009-2022
A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, t
Autor:
Montek Singh, Steven M. Nowick
Publikováno v:
IEEE Design & Test. 32:19-28
This two-part article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art. Part 1 covered foundations of asynchronous design, and highlighted recent applications, includ
Autor:
Steven M. Nowick, Montek Singh
Publikováno v:
IEEE Design & Test. 32:5-18
An asynchronous design paradigm is capable of addressing the impact of increased process variability, power and thermal bottlenecks, high fault rates, aging, and scalability issues prevalent in emerging densely packed integrated circuits. The first p
Publikováno v:
NOCS
Multicast communication (1-to-many) is common in parallel architectures and emerging areas such as neuromorphic computing. However, there is very limited research in supporting multicast in asynchronous NoCs. This paper proposes a new parallel multic
Publikováno v:
NGCAS
Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous int