Zobrazeno 1 - 10
of 25
pro vyhledávání: '"M. MISCIONE"'
Publikováno v:
IEEE Transactions on Electron Devices. 58:3787-3792
The off-state source-to-drain leakage current and punchthrough voltage are the quantities that frequently limit the performance of short-channel floating-body silicon-on-sapphire (SOS) n-channel MOSFETs. In this paper, we demonstrate that the high-te
Il saggio prende in esame l’evoluzione delle fonti interne del diritto del lavoro. L’attenzione è rivolta all’ampliamento delle competenze legislative delle Regioni, come stabilito dalla l. costituzionale n. 3 del 2001, al ruolo dell’autonom
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______4094::57116d54fb95b02f8962b0b3b913b2cf
http://hdl.handle.net/11585/59565
http://hdl.handle.net/11585/59565
Autor:
K. Bernstein, P. Dao, B. Anthony, L. Union, D. Kolar, J. Brenizer, J. Lin, T.R. White, C. Apblett, A. Chase, V. Sheth, M. Miscione
Publikováno v:
10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295).
Described is an essentially all electronic defect inspection, management, and reporting system, integrating defect data, images, and bit maps. It is shown how the system increases the efficiency of inline defect monitoring by utilizing ADC, allowing
Autor:
John Damiano, H. Tian, M. Miscione, K. Cox, E. Deeters, C. Feng, M. Gibson, H. Nguyen, L. Zeng, M. Blackwell, C. Honcik, Y.-S. Feng, J. R. Zaman, J. Scott, J. Sebek, T. McNelly, James D. Hayden, C.K. Subramanian
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. Trench dislocations in a 0.25 /spl mu/m BiCMOS SRAM technology were traced to defects arising during S/D processing. It is argued that these defects coalesce to form dislocations, typically near the trench edge, under the com
Publikováno v:
Journal of Orthopaedics & Traumatology; Sep2007, Vol. 8 Issue 3, p128-133, 6p
Publikováno v:
IEEE Transactions on Nuclear Science. 34:1431-1437
The dependence of latch-up sensitivity in 1.25 μm p-well, CMOS devices on layout parameters, backside contacts, and thickness of epitaxial layers has been investigated by analysis and testing using a specially designed test chip. Retrograde wells an
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