Zobrazeno 1 - 10
of 57
pro vyhledávání: '"M. Lerme"'
Publikováno v:
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. 16:1604-1608
Two types of plasma source, high density plasma and magnetically enhanced reactive ion etching, have been compared on contact and vias etch process performances for 0.25 μm complementary metal–oxide semiconductor technology application. High densi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09709fae138ed2efb954d3dad36b59c9
https://doi.org/10.1116/1.581127
https://doi.org/10.1116/1.581127
Publikováno v:
Microelectronic Engineering. 19:13-16
SILO process with R.T.N. of silicon is an alternative isolation scheme, which provides both small field encroachment and rigorous isolation with 0.8 μm active area spacing. Two field doping processes were developed for 0.5 μm CMOS technology and we
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5bf192cdf6841046c7b85bd7be7a12b
https://doi.org/10.1016/0167-9317(92)90384-4
https://doi.org/10.1016/0167-9317(92)90384-4
Publikováno v:
Microelectronic Engineering. 15:647-650
A complete process for field isolation, applicable to a 0.5 μm CMOS technology, has been developed using SILO process with Rapid Thermal Nitridation of Silicon (R.T.N.). Adequate isolation was achieved for 0.9 μm active area spacing and n+ to p+ di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fc2ed3d7bdf948bdbb6551b8b88b68e
https://doi.org/10.1016/0167-9317(91)90302-t
https://doi.org/10.1016/0167-9317(91)90302-t
Autor:
M. Guerin, M. Lerme, Simon Deleonibus, F. Vinet, C. Jaffard, G. Reimbold, G. Guegan, C. Leroux, M. Belleville, M. Heitzmann, François Martin
Publikováno v:
Microelectronic Engineering. 15:257-260
An advanced high performance 0.5 μm technology for fast CMOS circuits has been developed. The main features for this 0.5 μm technology include : diffused wells, field isolation with a SILO/RTN process, N+ polysilicon gate, TaSi2 gate material, cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57697fdeb02f93ab1300ea970293c9e7
https://doi.org/10.1016/0167-9317(91)90224-2
https://doi.org/10.1016/0167-9317(91)90224-2
Publikováno v:
IEEE Transactions on Electron Devices. 38:1832-1839
Experimental observations that depletion-mode MOS devices optimized for room temperature can also work well when immersed in liquid nitrogen are reported in which the classical impurity freeze-out effect seems to vanish on short-channel devices if th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ee88a99af7d10b7165301a808914b5f
https://doi.org/10.1109/16.119022
https://doi.org/10.1109/16.119022
Publikováno v:
Microelectronic Engineering. 11:507-514
A new positive working system for deep UV and E-beam lithography, called PRIME ( p ositive r esist im age by dry e tching) using silylation and dry development is proposed. This paper will first compare PRIME to other dry developed processes such as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::009dc6c65ac68a7fac204a236e17f0d9
https://doi.org/10.1016/0167-9317(90)90160-u
https://doi.org/10.1016/0167-9317(90)90160-u
Publikováno v:
1996 IEEE International SOI Conference Proceedings.
Fully-depleted (FD) 0.2 /spl mu/m SOI CMOS devices have been fabricated with a single N+ gate process. As an ultra-thin film is required to optimize fully-depleted 0.2 /spl mu/m SOI devices, a recessed channel structure has been used in order to prev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c256566b4c8a1aa1a157066aebc30aed
https://doi.org/10.1109/soi.1996.552503
https://doi.org/10.1109/soi.1996.552503
Autor:
Simon Deleonibus, C. Jaffard, M. Heitzmann, G. Guegan, S. Tedesco, Charles Leroux, M. Lerme, G. Reimbold, M. Guerin, M. Belleville, François Martin
Publikováno v:
International Electron Devices Meeting 1991 [Technical Digest].
Advanced high-performance CMOS circuits with 0.35 mu m gate length were developed using mixed e-beam/optical lithography. These circuits have been processed with the following features: field isolation with a SILO/RTN (sealed interface local oxidatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eaa09964e7bd545ef7c3618718dbbd03
https://doi.org/10.1109/iedm.1991.235413
https://doi.org/10.1109/iedm.1991.235413
Publikováno v:
IEEE Electron Device Letters. 12:667-669
Polycide-gate silicon n-channel MOSFETs were fabricated on the basis of a standard 0.5- mu m MOS technology and measured over the 1.5-26.5-GHz frequency range, in order to investigate the effects of channel-length reduction on device behavior at high
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::167f894de1ed9ca4a9eb3596086b2e17
https://doi.org/10.1109/55.116949
https://doi.org/10.1109/55.116949
Autor:
Charles Le Cornec, M. Lerme, Thierry Mourier, Fabienne Baudru, Francoise Vinet, M. Laurens, Bernard Guillaumot
Publikováno v:
SPIE Proceedings.
The new microelectronics devices' generations require an increase in resolution down to 0.35 micrometers . For this purpose, deep UV lithography appears to be a good candidate. Excimer laser deep UV steppers have matured to a production worthy state.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::715b0c2ec561af44c67ea2ef86142c72
https://doi.org/10.1117/12.150473
https://doi.org/10.1117/12.150473