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pro vyhledávání: '"M. Kakumu"'
Akademický článek
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Akademický článek
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Publikováno v:
IEEE Transactions on Electron Devices. 47:178-186
In this paper, we present the results of optimizing interconnect parameters to satisfy chip-level targets in future device generations. The optimization approach used is based on existing system-level models and can optimize the number of wire levels
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f967fcf859ac7223bff3fb798494e3b6
https://doi.org/10.1109/16.817584
https://doi.org/10.1109/16.817584
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17:1252-1261
The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI) necessitates the development of new processes and tools for almost every device generation. Since such development usua
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70e146debbd25152f1d85da414387fc8
https://doi.org/10.1109/43.736565
https://doi.org/10.1109/43.736565
Publikováno v:
IEEE Transactions on Electron Devices. 39:370-378
The design optimization for 0.3- mu m channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daa4c22870433f863d304fe5fcc9a17d
https://doi.org/10.1109/16.121696
https://doi.org/10.1109/16.121696
Publikováno v:
IEEE Transactions on Electron Devices. 37:1334-1342
The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for opti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::623096fbf29577b671abb5678735c7ca
https://doi.org/10.1109/16.108196
https://doi.org/10.1109/16.108196
Autor:
M. Kakumu, M. Kinugawa
Publikováno v:
IEEE Transactions on Electron Devices. 37:1902-1908
Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea69a8c7126d03bd940130b98f6ac8db
https://doi.org/10.1109/16.57142
https://doi.org/10.1109/16.57142
Publikováno v:
International Electron Devices Meeting. Technical Digest.
This paper proposes a new plasma damage model that can explain and estimate the plasma damage in a CMOS LSI by taking into account the additional factor of pattern density. Reliability data presented in this paper shows that plasma damage to MOSFET g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fe28ed1bdecd7240d81095d6712087a
https://doi.org/10.1109/iedm.1996.554086
https://doi.org/10.1109/iedm.1996.554086
Publikováno v:
Proceedings of 1996 International Symposium on Low Power Electronics and Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9abbca5f6722fe13fcc7d1714768148
https://doi.org/10.1109/lpe.1996.547530
https://doi.org/10.1109/lpe.1996.547530
Autor:
T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b14df6348bca1a0342c45274a4fc272f
https://doi.org/10.1109/isscc.1996.488555
https://doi.org/10.1109/isscc.1996.488555