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pro vyhledávání: '"M. Janai"'
MirrorBit ® technology (also known as NROM) is a unique localized charge-trapping based non-volatile memory device that employs two separate physical and narrow charge packets per transistor, enabling two bits per cell. This technology requires a st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::197682eb0d41bdf41c932b231cf68946
https://doi.org/10.1016/b978-0-12-803581-8.01768-9
https://doi.org/10.1016/b978-0-12-803581-8.01768-9
Autor:
Meng Chuan Lee, M. Janai
Publikováno v:
IEEE Transactions on Electron Devices. 59:596-601
Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by high-temperature bake shifts the mean Vt of programmed bits and increases the variance of the Vt distribut
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 4:397-403
Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM technology is able to provide code flash, data flash, embedded flash, and true EEPROM functionalit
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 4:404-415
Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temper
Publikováno v:
IEEE Electron Device Letters. 31:1038-1040
Different charge-gain (CG) processes are reported in EEPROM nonvolatile Flash memory devices. The process originally characterized in nitride-trapping devices is reexamined. Its mechanism is reinterpreted in terms of the recovery of negative-bias tem
Autor:
J. Neo, S. Ortiz, T. Fang, D. Matsumoto, F. Tsai, Unsoon Kim, James Pak, S. Bell, Y. Sun, G. Nagatani, Timothy Thurgate, Sameer Haddad, M. Janai, Inkuk Kang, S. Shetty, P.K. Singh, Calvin Gabriel, Rinji Sugino, A. Samqui, S. Tehrani, Mark T. Ramsbey, Kuo-Tung Chang, Chun Chen, Shenqing Fang, Angela Hui
Publikováno v:
2013 5th IEEE International Memory Workshop.
For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product performance, reliability, and manufacturability demonstrated at the 43nm node, in conjunction with t
Publikováno v:
Optics letters. 2(2)
Photolithography by light-enhanced vaporization (LEV) of thin films of amorphous As2S3 is described. Diffraction gratings were produced by laser double-beam interference patterns recorded on the As2S3 thin film using the LEV process. The gratings wer
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster than electron relaxation. The degradation of data retention in cycled NROM cells is interprete
Publikováno v:
Encyclopedia of Materials: Science and Technology ISBN: 9780080431529
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0a2de6f11ff50ffd8c6109130d12f89e
https://doi.org/10.1016/b978-008043152-9/02181-3
https://doi.org/10.1016/b978-008043152-9/02181-3
Autor:
Boaz Eitan, R. Sahar, A. Lavan, Y. Polansky, Eli Lusky, Guy Cohen, A. Givant, Eduardo Maayan, O. Dadashev, M. Janai, Assaf Shappir, Ilan Bloom
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming alg