Zobrazeno 1 - 10
of 77
pro vyhledávání: '"M. Inohara"'
Autor:
Y Kashima, Y Naka, T Furusato, M Inohara, Kazuhiro Morishita, K Nozaki, Koji Matsuno, H Kimura, S Matsuoka, Yoshihiro Uesawa, Yoshihito Okada, Hisahiro Kai
Publikováno v:
67th International Congress and Annual Meeting of the Society for Medicinal Plant and Natural Product Research (GA) in cooperation with the French Society of Pharmacognosy AFERP.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::579a4e929719e35d24a3d170ae2ceffc
https://doi.org/10.1055/s-0039-3399827
https://doi.org/10.1055/s-0039-3399827
Autor:
M. Inohara, Yoshiaki Toyoshima
Publikováno v:
IEEE Transactions on Electron Devices. 52:2634-2639
The demand for higher current density in metal interconnects continues to increase to meet the challenges of higher operation frequency and the more complex design requirement of deep submicrometer integrated circuits. However, improvement in the all
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b20997082c43578a1cf42f4ca52e9592
https://doi.org/10.1109/ted.2005.859640
https://doi.org/10.1109/ted.2005.859640
Publikováno v:
Journal of Bioscience and Bioengineering. 90:535-539
To examine the role of His452 of the Saccharopolyspora rectivirgula beta-galactosidase in the binding of a tightly bound, catalytically important Mn2+ (i.e., class II Mn2+) ion, His452 was replaced with Phe or Glu and the respective site-directed mut
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::35943863b92a3c3fddc883f24a2b6040
https://doi.org/10.1263/jbb.90.535
https://doi.org/10.1263/jbb.90.535
Publikováno v:
Journal of Biological Chemistry. 269:22021-22026
To understand the roles of metal ions on the catalytic properties and thermostability of the thermostable beta-galactosidase of Saccharopolyspora rectivirgula, a thermophilic actinomycete, we have investigated the binding kinetics and requirements of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9dd446e6c49e42790fc87d0a021c78c6
https://doi.org/10.1016/s0021-9258(17)31749-0
https://doi.org/10.1016/s0021-9258(17)31749-0
Autor:
M. Inohara, T. Watanabe, T. Kitano, Y. Nakahara, N. Matsunaga, E. Hasegawa, Y. Kitamura, S. Hasegawa, S. Muramatsu, S. Nagahara, G. Tsutsui, H. Harakawa, T. Ishizuka, H. Okamoto, N. Okada, M. Satake, H. Aizawa, Y. Suzuki, Kazuaki Nakajima, K. Takeda, T. Fukushima, T. Hirai, S. Mimotogi, S. Aota, Atsushi Azuma, H. Onoda, K. Miyashita, T. Oki, K. Nakatsuka, T. Nakayama, Y. Goto, K. Taniguchi, K. Takahata, S. Okamoto, R. Ogawa, K. Utsumi, S. Watanabe, M. Tanaka, M. Tagami, K. Okano, K. Kojima, Y. Yoshimizu, Fumiyoshi Matsuoka, N. Nakamura, T. Iwamoto, A. Nomachi, M. Tominaga, K. Nagatomo, S. Inumiya, T. Komukai, T. Ishida, H. Naruse, M. Nishigoori, T. Suzuki, N. Kariya, T. Sasaki
Publikováno v:
2008 IEEE International Electron Devices Meeting.
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7eb86e67686bfb13ad57ca9b67b74180
https://doi.org/10.1109/iedm.2008.4796776
https://doi.org/10.1109/iedm.2008.4796776
Autor:
H. Igrashi, Hisao Yoshimura, Keiichiro Yoshida, M. Iwai, A. Oishi, Kazuaki Okamoto, Fumiyoshi Matsuoka, Kiyotaka Imai, T. Nakayama, Y. Nakahara, K. Honda, Sachiko Kobayashi, Koichi Kinoshita, T. Hirai, Toyota Morimoto, Naofumi Nakamura, Toshiyuki Iwamoto, Eiji Morifuji, T. Sanuki, H. Kimijima, S. Miyake, M. Ikeda, S. Kyoh, Fujita Shinobu, K. Kojima, H. Otani, H. Fukui, R. Watanabe, M. Inohara
Publikováno v:
2008 IEEE International Electron Devices Meeting.
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realiz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a2faab0793ced2af1e6943aa77ba2a58
https://doi.org/10.1109/iedm.2008.4796773
https://doi.org/10.1109/iedm.2008.4796773
Autor:
S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, Dureseti Chidambarrao
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19c3a590b7034d81db7315743b8ecea4
https://doi.org/10.1109/.2005.1469238
https://doi.org/10.1109/.2005.1469238
Autor:
Sachiyo Ito, Takashi Yoda, H. Kamijo, M. Inohara, T. Hachiya, K. Akiyama, K. Tabuchi, Hideki Shibata, K. Watanabe, Hideshi Miyajima, K. Higashi, Shingo Kadomura, N. Matsunaga, Hisashi Yano, Akihiro Kajita, Nobuo Hayasaka, Toshiaki Hasegawa, Katsuyuki Fujita, R. Kanamura, T. Shimayama, Y. Enomoto, Rempei Nakata, K. Honda, Naofumi Nakamura
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b28caa227e5631f359cdcb93781cbf72
https://doi.org/10.1109/iedm.2004.1419147
https://doi.org/10.1109/iedm.2004.1419147
Autor:
Hidetoshi Koike, Shingo Kadomura, K. Sunouchi, Y. Enomoto, S. Arakawa, I. Tamura, M. Inohara, T. Watanabe, Takeshi Yamaguchi, E. Ide
Publikováno v:
Digest. International Electron Devices Meeting.
Dual damascene copper and low-k (k=2.9) interconnect technology for 90nm-node was successfully integrated. Structure and process are optimized to be compatible to transistor, memories, and packaging with consideration of RC delay and crosstalk betwee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a87afcad891134ae0df27bcd096b3c4f
https://doi.org/10.1109/iedm.2002.1175783
https://doi.org/10.1109/iedm.2002.1175783
Autor:
K. Miyamoto, M. Inohara, Keiichiro Yoshida, T. Fujimaki, T. Katata, Fumiyoshi Matsuoka, Junichi Wada, A. Sakata, A. Kinoshita
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
A copper filling contact process that does not cause any device characteristic degradation or reliability degradation is demonstrated. Optimization of the barrier layer realizes lower and small variation contact resistance with enough prevention of c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ad566c550b5583907e70cdd9ff264b2
https://doi.org/10.1109/iedm.2001.979667
https://doi.org/10.1109/iedm.2001.979667