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A novel 2-Dimensional correction method for mm-Wave Cartesian I/Q Modulators

Autor: M. Ganzerli, Maarten Lont, Kostas Doris, P. Athanasiadis, M. Neofytou, Georgi Radulov

Publikováno v: ISCAS
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021-Proceedings

This paper proposes a self-corrected In-phase/Quadrature-phase (I/Q) digital Cartesian modulator. The modulator is comprised of double balanced Gilbert cells to mitigate code dependent input and output impedances. Transistor-level simulations in 28 n

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::717cd425f19beff146ed3578e5755c90
https://research.tue.nl/en/publications/f6c57bf1-9e28-422f-8f1a-8e6ac53adce5

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Time Interleaved ADC mismatch error correction technique in I/Q Digital Beamforming Receivers

Autor: Kostas Doris, P. Athanasiadis, M. Neofytou, M. Ganzerli, Georgi Radulov

Publikováno v: 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021-Proceedings, 1-5
STARTPAGE=1;ENDPAGE=5;TITLE=2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021-Proceedings
ISCAS

Time-Interleaved ADCs are essential for new generation mm-wave digital beamforming receivers offering multi-GHz bandwidths for radar sensing or high data rate communication links. Timing mismatches is one of the main performance limitations of these

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b9e8d9da3f5e3d8e1111d4aaccfc9b67
https://research.tue.nl/nl/publications/6cce57cf-6a22-4506-b456-c0a235d549d0

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A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

Autor: Kofi A. A. Makinwa, M. Ganzerli, P. Cenci, Muhammed Bolatkale, Robert Rutten, Lucien J. Breems, G. Lassche

Publikováno v: VLSI Circuits
2019 Symposium on VLSI Circuits: Digest of technical papers
2019 Symposium on VLSI Circuits
2019 Symposium on VLSI Circuits, VLSI Circuits 2019-Digest of Technical Papers, C230-C231
STARTPAGE=C230;ENDPAGE=C231;TITLE=2019 Symposium on VLSI Circuits, VLSI Circuits 2019-Digest of Technical Papers

This paper presents a SAR-assisted Continuous-time Delta-Sigma $( \mathrm { CT } \Delta \Sigma )$ ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of $\mathrm { CT } \Delta \Sigma$ ADCs, as well as similar a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c01c6d0846598ed91c2c3fd0dd06dcbe
https://research.tue.nl/en/publications/732ae7d3-7b18-4ec3-8028-f6abff838dcf

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A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard

Autor: Jacopo Iannacci, Luca Larcher, Antonio Gnudi, Benno Margesin, Marco Bedani, M. Ganzerli, R. Brama

Publikováno v: Fondazione Bruno Kessler-IRIS

In this work we present a reconfigurable mid-power Class-E Power Amplifier (PA) operating at ~900MHz and ~1800MHz (GSM standard) realized hybridizing one chip manufactured in AMS 0.35µm CMOS technology and one MEMS sub-network. The CMOS chip realize

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d1096fbda18c0dbe57ba58320217144d
https://hdl.handle.net/11380/634702

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An Inductor-less 13.5-Gbps 8-mW Analog Equalizer for Multi-Channel Multi-Frequency Operation

Autor: M. Ganzerli, D. Sanzogni, Luca Larcher, Simone Erba

Publikováno v: ISCAS

A low-power analog equalizer has been realized in 45nm CMOS technology. Active feedback is employed to avoid inductors and save chip area. Peaking frequency and gain boost can be finely controlled from 4GHz to 7GHz and from 0dB to 24dB to allow multi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2d587f63480b06a02ae5431860186af1
https://hdl.handle.net/11380/650035

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