Zobrazeno 1 - 10
of 614
pro vyhledávání: '"M. Breitwisch"'
Autor:
D. K. Finnemore, M. Breitwisch
Publikováno v:
Physical Review B. 62:671-677
Artificial structures were intentionally introduced into Nb films in order to study the interaction of a single Abrikosov vortex with pinning sites caused by these known defects. A vortex trapped on one of these structures or defects can be induced t
Publikováno v:
Physical Review B. 60:10508-10512
Thermal depinning of a single vortex trapped in a superconducting thin film has been measured in order to study the Bean-Livingston surface barrier. There are two forces that bias the motion of the vortex in the natural pinning potential of the film.
Flux expulsion and reversible magnetization in the stripe phase superconductorLa1.45Nd0.40Sr0.15CuO4
Publikováno v:
Physical Review B. 56:2820-2823
Magnetization and free energy surfaces have been studied for superconducting La{sub 1.45}Nd{sub 0.40}Sr{sub 0.15}CuO{sub 4} in order to determine whether this stripe-phase material has a thermodynamic critical field curve, H{sub c}, similar to the cl
Publikováno v:
IEEE Transactions on Appiled Superconductivity. 7:1691-1694
The growth of hillocks at the interface between Bi(2212) and Ag has been found to occur over a wide range of oxygen partial pressure and in the vicinity of 700/spl deg/C, a temperature far below the Bi(2212)-Bi(2223) conversion temperature. These hil
Publikováno v:
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.
A method based on Frenkel-Poole emission is proposed to model the I–V data of the amorphous state (high resistance state) in mushroom-type phase-change memory (PCM) devices. We found the I–V characteristics in the high resistance state are domina
Autor:
null Sungjae Lee, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, N. Zamdmer, M. Breitwisch, R. Ramachandran, G. Freeman
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance. The effect of layout and geometry optimization as
Autor:
Go, Shao-Xiang1 (AUTHOR), Lim, Kian-Guan1 (AUTHOR), Lee, Tae-Hoon2,3 (AUTHOR), Loke, Desmond K.1 (AUTHOR) desmond_loke@sutd.edu.sg
Publikováno v:
Small Science. Mar2024, Vol. 4 Issue 3, p1-34. 34p.
Autor:
Stenz, Christian1 (AUTHOR) stenz@physik.rwth-aachen.de, Pries, Julian1 (AUTHOR), Surta, T. Wesley2 (AUTHOR), Gaultois, Michael W.3 (AUTHOR), Wuttig, Matthias1,4 (AUTHOR) wuttig@physik.rwth-aachen.de
Publikováno v:
Advanced Science. 12/27/2023, Vol. 10 Issue 36, p1-14. 14p.
Publikováno v:
Advanced Electronic Materials; Dec2024, Vol. 10 Issue 12, p1-15, 15p
Publikováno v:
RSC Advances; 2024, Vol. 14 Issue 41, p29812-29826, 15p