Zobrazeno 1 - 10
of 123
pro vyhledávání: '"M. Angyal"'
Autor:
V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. W. Jeong, Y. G. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbe
Publikováno v:
2023 35th International Conference on Microelectronic Test Structure (ICMTS).
Autor:
C.H. Lee, B.W. Jeong, S. Wu, M. Kim, X. Chen, K. Onishi, C. Manya, L. Anastos, J. Sim, M. Angyal
Publikováno v:
2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS).
Akademický článek
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Akademický článek
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Publikováno v:
Rechtsmedizin. 9:141-144
Aus der Summe der in der Praxis zur Verfugung stehenden Methoden zur rechtsmedizinischen Personenidentifikation untersuchten die Verfasser die Vorteile der radiologischen Identifizierungsmoglichkeiten unter radiologischen Bedingungen sowie deren Gren
Publikováno v:
International Journal of Legal Medicine. 108:150-153
Suicidal deaths which occurred in Baranya County, Hungary between 1983 and 1987 were investigated with regard to biodemographical aspects. The number of suicidal deaths for this period was 1056 and the rate for this region was higher in villages than
Autor:
C.-K. Hu, M. Angyal, B. C. Baker, G. Bonilla, C. Cabral, D. F. Canaperi, S. Choi, L. Clevenger, D. Edelstein, L. Gignac, E. Huang, J. Kelly, B. Y. Kim, V. Kyei-Fordjour, S. L. Manikonda, J. Maniscalco, S. Mittal, T. Nogami, C. Parks, R. Rosenberg, A. Simon, Y. Xu, T. A. Vo, C. Witt, Ehrenfried Zschech, Shinichi Ogawa, Paul S. Ho
Publikováno v:
AIP Conference Proceedings.
The impact of the existence of Cu grain boundaries on the degradation of Cu interconnect lifetime at the 45 nm technology node and beyond has suggested that improved electromigra‐tion in Cu grain boundaries has become increasingly important. In thi
Autor:
Anda Mocuta, M. Angyal, An L. Steegen, Vidhya Ramachandran, T. Hook, Dan Moy, Douglas D. Coolbaugh, Percy V. Gilbert
Publikováno v:
2007 IEEE International Electron Devices Meeting.
A common platform technology at 65 nm is described. The platform consists of a low-power CMOS base technology with a broad menu of optional features including high- performance passive devices, standard cell libraries, SRAM compilers and a process de
Autor:
S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, Dureseti Chidambarrao
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL en
Autor:
Chelsea Dang, A. Nghiem, Reena Tiwari, John Mendonca, W. Clark, Percy V. Gilbert, John L. Sturtevant, A. Das, E. Park, T. Sparks, H. De, T. McNelly, S. Veeraraghavan, E. Banks, B. Chu, M. Angyal, M. Kling, Mousumi Bhat, M. Woods, K. McGuffin, F. Huang, C. Feng, D. Rose, C. Pettinato, I. Yang, F. Nkansah, C. Fu, T. VanGompel, B. Boeck, K. Lucas, B. Roman
Publikováno v:
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
A high performance 0.10 /spl mu/m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 /spl mu/m-0.13 /spl mu/m gate length with physical 3 nm gate oxides and 0.175 /spl mu/m local interco