Zobrazeno 1 - 10
of 348
pro vyhledávání: '"M Ercken"'
Autor:
Philippe Leray, N. Jourdan, O. Varela Pedreira, E. Dentoni-Litta, Thomas Witters, Werner Gillijns, Nancy Heylen, L. Ramakers, E. Grieten, Zaid El-Mekki, Gayle Murdoch, V. Vega-Gonzalez, Anne-Laure Charley, Ivan Ciofi, Zsolt Tokei, H. Vats, S. V. Gompel, M. H. van der Veen, L. Halipre, J. Swerts, A. Haider, Bilal Chehab, S. Park, N. Bazzazian, Quoc Toan Le, B. De Wachter, T. Peissker, Harinarayanan Puliyalil, Naoto Horiguchi, Miroslav Cupak, J. Versluijs, G. T. Martinez, Y. Kimura, R. Kim, J. Geypen, J. Uk-Lee, N. Nagesh, D. Montero, L. Rynders, M. Ercken, D. Batuk, K. Croes, Patrick Verdonck, Manoj Jaysankar, Y. Drissi, T. Webers
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::775097fabe7d875876eeac9844668bb1
https://doi.org/10.1109/iitc51362.2021.9537535
https://doi.org/10.1109/iitc51362.2021.9537535
Autor:
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d5b5a73112c7be6f5016d4aa4c44eb7
https://doi.org/10.1109/iedm13553.2020.9372096
https://doi.org/10.1109/iedm13553.2020.9372096
Autor:
Nancy Heylen, K. Croes, Rogier Baert, S. Park, Geoffrey Pourtois, Jean-Philippe Soulie, Katia Devriendt, Christopher J. Wilson, Ming Mao, Q-T. Le, V. Blanco, Gayle Murdoch, Herbert Struyf, Anshul Gupta, V. Vega, Lieve Teugels, S. Paolillo, N. Jourdan, Kiroubanand Sankaran, J. Sweerts, Ivan Ciofi, S. Decoster, P. Morin, Els Kesters, Juergen Boemmels, Frederic Lazzarino, Zs. Tokei, Christoph Adelmann, M. H. van der Veen, M. Ercken, Kris Vanstreels, S. Van Elshocht, M. O'Toole, J. Versluijs, M. H. Na, Frank Holsteyns, Houman Zahedmanesh
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3b4b449b819b2556b63b50762bf16b9
https://doi.org/10.1109/iedm13553.2020.9371903
https://doi.org/10.1109/iedm13553.2020.9371903
Autor:
V. Vega-Gonzalez, J. Bekaert, E. Kesters, Q. T. Le, C. Lorant, O. Varela P., L. Teugels, N. Heylen, Z. El-Mekki, M. van der Veen, T. Webers, C. J. Wilson, H. Vats, L. Rynders, M. Cupak, J. Uk-Lee, Y. Drissi, L. Halipre, A.-L. Charley, P. Verdonck, T. Witters, S. V. Gompel, B. Briggs, Y. Kimura, N. Jourdan, I. Ciofi, A. Gupta, A. Contino, G. Boccardi, S. Lariviere, L. Dupas, B. De-Wachter, E. Vancoille, S. Decoster, F. Lazzarino, M Ercken, P. Debacker, R. Kim, D. Trivkovic, K. Croes, P. Leray, L. Dillemans, Y.-F. Chen, Z. Tokei, J. Versluijs, A. Lesniewska, S. Paolillo, R. Baert, H. Puliyalil
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7eecb12b8a386042eac7e3255fe54876
https://doi.org/10.1109/iedm19573.2019.8993538
https://doi.org/10.1109/iedm19573.2019.8993538
Autor:
Victor Blanco, Gayle Murdoch, S. Paolillo, Danny Wan, Christoph Adelmann, Bogumila Kutrzeba Kotowska, Nouredine Rassoul, Frederic Lazzarino, Christopher J. Wilson, Jürgen Bömmels, Zsolt Tokei, M. Ercken
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
Ruthenium has been recently considered as a promising candidate to replace copper as the BEOL interconnect material for sub-5nm technology nodes. In this work, single level Ru interconnects were fabricated in imec's 300-mm pilot line using EUV lithog
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87ff871b8552326059f2788385084bb2
https://doi.org/10.1109/iitc.2018.8454841
https://doi.org/10.1109/iitc.2018.8454841
Autor:
E. Dentoni Litta, R. Ritzenthaler, T. Schram, A. Spessot, B. O'Sullivan, Y. Ji, G. Mannaert, C. Lorant, F. Sebaai, A. Thiam, M. Ercken, S. Demuynck, N. Horiguchi
Publikováno v:
Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ad113f1a8aff2d01c775534795d762d
https://doi.org/10.7567/ssdm.2017.k-4-02
https://doi.org/10.7567/ssdm.2017.k-4-02
Autor:
Adrien Vaysset, Eline Raymenants, Khashayar Babaei Gavan, Iuliana Radu, Kristof Paredis, Danny Wan, Cedric Huyghebaert, Dan Mocuta, A. Thiam, Christopher J. Wilson, Johan Swerts, Nouredine Rassoul, J. Jussot, Lennaert Wouters, Safak Sayan, Mauricio Manfrini, Sebastien Couet, M. Ercken, Laurent Souriau
Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7f482f0293f383448c4a4e167788300c
Autor:
Erik Rosseel, Julien Ryckaert, Efrain Altamirano-Sanchez, Philippe Matagne, T. Huynh-Bao, Katia Devriendt, Vasile Paraschiv, Adrian Chasin, Bertrand Parvais, Tsvetan Ivanov, Aaron Thean, A. Sibaja-Hernandez, Z. Tao, J. Versluijs, Eddy Simoen, Anabela Veloso, E. Vecchio, O. Richard, Boon Teik Chan, M. Ercken, B. Kaczer, Samuel Suhard, Stephan Brus, K. De Meyer, S. Ramesh, C. Delvaux, Nadine Collaert, Hugo Bender, P. Lagrain, Niamh Waldron
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I OFF values and excellent electrostatics can be obtained with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f64b857c9947bedfab2383d329a1f103
https://doi.org/10.1109/vlsit.2016.7573409
https://doi.org/10.1109/vlsit.2016.7573409
Autor:
Guglielma Vecchio, Pieter Blomme, Laurent Sourieau, H. Hody, Janko Versluis, Jan Van Houdt, Chi Lim Tan, Geert Van den bosch, Vasile Paraschiv, M. Ercken
Publikováno v:
2016 IEEE 8th International Memory Workshop (IMW).
We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid poly\metal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully pla
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cca3fa09ee5485ec9ad4d24c5411368a
https://doi.org/10.1109/imw.2016.7495282
https://doi.org/10.1109/imw.2016.7495282
Autor:
Stephan Brus, S. Verhaegen, Efrain Altamirano-Sanchez, Anabela Veloso, C. Delvaux, M. Ercken, Christina Baerts, Marc Demand, T. Vandeweyer, J. De Backer, S. Locorotondo, Naoto Horiguchi
Publikováno v:
Microelectronic Engineering. 87:993-996
FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22nm node 6T-SRAM cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9483254ad9233fa51abceefc7885662d
https://doi.org/10.1016/j.mee.2009.11.119
https://doi.org/10.1016/j.mee.2009.11.119