Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Luqiang Duan"'
Autor:
Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:411-427
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::773d8e33a870a7c253213c238232f9a4
https://doi.org/10.1109/jssc.2022.3185160
https://doi.org/10.1109/jssc.2022.3185160
Autor:
Xiangrong Huang, Shengnan Dong, Pingda Guan, Wei Deng, Baoyong Chi, Taikun Ma, Zhihua Wang, Ruichang Ma, Guopei Chen, Luqiang Duan, Shiyan Sun, Haikun Jia, Zipeng Chen
Publikováno v:
VLSI Circuits
A D-band radar/communication fusion-mode transceiver featuring dual-function multiplexers, a two-point modulation (TPM) FMCW digital PLL with a dual-core DCO, wideband I/Q LO generators, current choking high-gain mixers, and a power-combining PA with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dce2d2cc6e632d38bcf25aefb8a9fce1
https://doi.org/10.23919/vlsicircuits52068.2021.9492460
https://doi.org/10.23919/vlsicircuits52068.2021.9492460
Publikováno v:
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
A highly linear 3rd-order active-RC low-pass filter with 30MHz -3dB bandwidth in 28nm CMOS is presented. Since the power supply in 28nm CMOS has been reduced to 0. 9V, there are many challenges in the design of analog circuits. Common-mode level-shif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e35b3e22acdcb9a6c2c6d504b43ac59a
https://doi.org/10.1109/edssc.2019.8754143
https://doi.org/10.1109/edssc.2019.8754143
Publikováno v:
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
An optimized Ka-band low noise amplifier (LNA) for phased array radar system is presented in this paper. Two gain-boosting techniques are quantitatively analyzed and employed on the proposed LNA to achieve high gain and low noise performances. Meanwh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b59702d2a531d40f7ce1dd4339d3650c
https://doi.org/10.1109/edssc.2019.8754111
https://doi.org/10.1109/edssc.2019.8754111
Publikováno v:
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
A dual-mode clock and data recovery (CDR) circuit based on phase interpolator (PI) in 65nm CMOS is presented. CDR can recover clock from quadrature phase shift keying (QPSK) modulated signal in non-to-zero (NRZ) mode, and 16 quadrature amplitude modu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b04b0efa74a6be642652c6628bb6938
https://doi.org/10.1109/edssc.2019.8754128
https://doi.org/10.1109/edssc.2019.8754128
Publikováno v:
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
A 47GHz frequency-modulated continuous-wave (FMCW) radar is presented. A current DAC with a 10bit 1st $\Sigma \Delta$ modulator is utilized to improve the equivalent DCO frequency resolution. A type-II PLL with the polarity-alternation is proposed to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58e0e38d7273257fe3ad373b195e1f6a
https://doi.org/10.1109/edssc.2019.8754050
https://doi.org/10.1109/edssc.2019.8754050