Výsledky vyhledávání - "Luis A. C. Benites"

Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects

Autor: Luis A. C. Benites, Nemitala Added, Fabio Benevenuti, Nilberto H. Medina, Adria Barros de Oliveira, Marcilei A. G. Silveira, Fernanda Lima Kastensmidt, Lucas A. Tambara, V. A. P. Aguiar

Publikováno v: Repositório Institucional da USP (Biblioteca Digital da Produção Intelectual)
Universidade de São Paulo (USP)
instacron:USP

This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::648897fe7a0ec74ceffedf45830b1fad
https://doi.org/10.1109/tns.2020.2995729

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Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

Autor: Adria Barros de Oliveira, Nilberto H. Medina, Fabio Benevenuti, Vitor A. P. Aguiar, M. A. Guazzelli, Fernanda Lima Kastensmidt, Nemitala Added, Luis A. C. Benites

Publikováno v: IEEE Transactions on Nuclear Science. 66:1433-1440

This paper presents comparative results from fault injection (FI) and heavy ions accelerated irradiation on a Xilinx 7 series static RAM (SRAM)-based field-programmable gate array (FPGA) for a soft-core microprocessor mitigated by triple modular redu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::422a6c09c1c9b829b3fc3dd264eb4afb
https://doi.org/10.1109/tns.2019.2921796

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Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

Autor: Luis A. C. Benites, Mayler G. A. Martins, Samuel Pagliarini, Fernanda Lima Kastensmidt, Paolo Rech

Publikováno v: IEEE Transactions on Nuclear Science

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multipl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c220b0202a9e26e9304f49f4b74d3154
http://hdl.handle.net/11583/2883396

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Analyzing the Influence of using Reconfiguration Memory Scrubber and Hardware Redundancy in a Radiation Hardened FPGA under Heavy Ions

Autor: V. A. P. Aguiar, Fabio Benevenuti, Adria Barros de Oliveira, Cedric Debarge, Gennaro S. Rodrigues, Nilberto H. Medina, Marcilei A. G. Silveira, Fernanda Lima Kastensmidt, Nemitala Added, Luis A. C. Benites

Publikováno v: 2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

This work investigates the influence of using the built-in configuration memory scrubber and triple modular hardware redundancy in the cross section of a radiation-hardened SRAM-based FPGA from NanoXplore. Different designs versions are investigated

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::937fbb6a4acb38fa45bec0b86b9919fc
https://doi.org/10.1109/radecs45761.2018.9328683

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Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits

Autor: Luis A. C. Benites, Fernanda Lima Kastensmidt

Publikováno v: LATS

This work intends to overcome the issues encountered in the use of commercial EDA tools to design fault-tolerant circuits based on the Triple Modular Redundancy (TMR) technique. Circuit optimizations performed by the tool tend to remove the added red

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::576ffae056749e083bd3712c0f82566f
https://doi.org/10.1109/latw.2018.8349668

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Fault injection methodology for single event effects on clock-gated ASICs

Autor: Fernanda Lima Kastensmidt, Luis A. C. Benites

Publikováno v: LATS

The power density of integrated circuits increases with the technology scaling, so the need of implementing low-power designs is increasing. The clock gating technique is typically employed to reduce the dynamic power consumption in digital integrate

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b024932c5b307d11b500982b1e84994f
https://doi.org/10.1109/latw.2017.7906742

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Dynamic heavy ions SEE testing of NanoXplore radiation hardened SRAM-based FPGA: Reliability-performance analysis

Autor: Lucas A. Tambara, Fabio Benevenuti, M. A. Guazzelli, Fernanda Lima Kastensmidt, Luis A. C. Benites, V. A. P. Aguiar, Nilberto H. Medina, Adria Barros de Oliveira, Gennaro S. Rodrigues, Nemitala Added

Publikováno v: Microelectronics Reliability. :113437

NanoXplore is the European pioneer vendor to develop ITAR-free radiation-hardened SRAM-based FPGAs. This work is the first to explore dynamic SEE tests in the NG-Medium FPGA device. The reliability-performance analysis of an embedded unmitigated desi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::46d395bf45f4366605328fc0fd5cb107
https://doi.org/10.1016/j.microrel.2019.113437

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