Zobrazeno 1 - 10
of 158
pro vyhledávání: '"Luigi Pantisano"'
Publikováno v:
ACI Avances en Ciencias e Ingenierías, Vol 2, Iss 2 (2010)
In this article we investigate the major problem of the micro/nano-electronic: How to reduce the Equivalent Oxide Thickness (EOT) in the sub-nanometric range and improving the MOSFET performance? To reduce the EOT it is necessary that the semicondu
Externí odkaz:
https://doaj.org/article/66800ae399fa450988da06a61bb3c903
Autor:
Andreas Kerber, B. Min, Maria Toledano-Luque, K. Nagahiro, S. Cimino, Zakariae Chbili, P. Paliwoda, Durgamadhab Misra, T. Nigam, Luigi Pantisano
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 19:249-254
This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due to SH is only significant for logic PFETs at highly accelerated d
Autor:
Y. Chen, S. V. Khokale, Vinayak Mahajan, W.L. Oo, Luigi Pantisano, Ali Razavieh, Man Gu, T. H. Lee, J. Lemon, Wang Haiting, Tamilmani Ethirajan, S. Cimino, K. Nagahiro
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
FinFET with contact over active-gate (COAG) is implemented on 12nm node technology platform to optimize the Maximum Oscillation Frequency $(F_{MAX})$ ) and the Minimum Noise Figure $(NF_{MIN}$ for devices with large fin numbers. This study shows that
Autor:
A. Gupta, P. Yee, O. H. Gonzalez, T. Nigam, M. Nour, P. Paliwoda, D. Ioannou, Michael J. Hauser, L. Jiang, Luigi Pantisano, S. Cimino, Fernando Guarin, B. Min, Maria Toledano-Luque, David A. Lee, A. Vayshenker, Stewart E. Rauch, W. Liu
Publikováno v:
NATW
This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results
Autor:
Meng Zhu, Yifan Liang, Aritra Dasgupta, Luigi Pantisano, Shahab Siddiqui, Manasa Medikonda, Jinghong Li, Balaji Kannan, Yibin Zhang, Merve Ozbek, Jinping Liu
Publikováno v:
ECS Transactions. 85:131-136
Autor:
Luigi Pantisano, Balaji Kannan, Merve Ozbek, Chu Tao, Purushothaman Srinivasan, A. Zainuddin, Sefa Dag, Kai Zhao, Murali Kota, Tae-hoon Kim, P. Paliwoda, Mohit Bajaj, M. Hasanuzzaman
Publikováno v:
Microelectronic Engineering. 178:258-261
Next generation finfet technology nodes will increasingly rely on the effective workfunction tuning to achieve the desired transistor VT as finfet doping is increasingly ineffective as a mean to tune VT. This work deals with metal gate workfunction e
Autor:
David Burnett, X. Zhang, E. Geiss, Ram Asra, El Mehdi Bazizi, Mitsuhiro Togo, H. Lazar, O. Kwon, Edmund Banghart, Jae Gon Lee, J. Versaggi, S. Yamaguchi, Owen Hu, D. K. Sohn, Palanivel Balasubramaniam, Srikanth Samavedam, Luigi Pantisano, Mohd Khair Hassan, H-C. Lo, B. Cohen, Hong Yu, H. S. Yang
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to r
Autor:
Y. Y. Chen, Sofie Mertens, Stefan Kubicek, Dirk Wouters, V.V. Afanasiev, Guido Groeseneken, J. Swerts, Bogdan Govoreanu, Ludovic Goux, Jorge A. Kittl, N. Jossart, Luigi Pantisano, B. Verbrugge, X.P. Wang, Vasile Paraschiv, Robin Degraeve, L. Altimime, Christoph Adelmann, Malgorzata Jurczak
Publikováno v:
Microelectronic Engineering. 112:92-96
We proposed a new, simpler, and fully BEOL CMOS-compatible TiN/HfO2/TiN RRAM stack using the Plasma Enhanced Atomic Layer Deposition (PEALD) for the top-electrode TiN processing, demonstrating attractive bipolar switching properties (by positive RESE
Autor:
Ivan Gordon, Luigi Pantisano, Twan Bearda, Andre Stesmans, Valery V. Afanas'ev, N.H. Thoan, Barry O'Sullivan, Mihaela Jivanescu, Frederic Dross, J. Poortmans
Publikováno v:
Energy Procedia. 27:185-190
In this work, an extensive characterisation of intrinsic amorphous silicon (a-Si) passivation layers deposited on n- and p-type silicon is reported. Low temperature capacitance-voltage measurements are utilised to enable parameter extraction from the
Autor:
Luigi Pantisano, Purushothaman Srinivasan, Eddy Simoen, Gino Giusi, Calogero Pace, Felice Crupi, V.R. Rao, Paolo Magnone, Cor Claeys, D. Maji
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 9:180-189
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We