Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Ludovic Ecarnot"'
Autor:
Sebastien Sollier, Julie Widiez, Gweltaz Gaudin, Frederic Mazen, Thierry Baron, Mickail Martin, Marie-Christine Roure, Pascal Besson, Christophe Morales, Elodie Beche, Frank Fournel, Sylvie Favier, Amelie Salaun, Patrice Gergaud, Maryline Cordeau, Christellle Veytizou, Ludovic Ecarnot, Daniel Delprat, Ionut Radu, Thomas Signamarcheix
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 6, Iss 4, p 19 (2016)
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low tempera
Externí odkaz:
https://doaj.org/article/ffe38044688c423db103fb20f61af151
Autor:
C. Sciancalepore, Quentin Wilmart, Ludovic Ecarnot, D. Herisson, Guillaume Chabanne, Bertrand Szelag, Aziz Alami-Idrissi
Publikováno v:
Smart Photonic and Optoelectronic Integrated Circuits 2022.
Autor:
Sachin Yadav, Yuye Kang, Manuel Sellier, Yida Li, Xiao Gong, Maheswari Sivan, Walter Schwarzenbach, Dian Lei, Christophe Maleville, Ludovic Ecarnot, Eugene Y.-J. Kong, Bich-Yen Nguyen, Aaron Thean
Publikováno v:
IEEE Transactions on Electron Devices. 66:2068-2074
Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSO
Autor:
Walter Schwarzenbach, Bich-Yen Nguyen, Ionut Radu, Anne Vandooren, Gweltaz Gaudin, Nadine Collaert, G. Besnard, Ludovic Ecarnot
Publikováno v:
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
Sequential or monolithic 3D integration requires a combination of advanced manufacturing processes and highly reliable integration scheme at both device and substrate level. In order to achieve this, front-end layer transfer technology looks as key e
Autor:
E. Cela, Christophe Maleville, Ludovic Ecarnot, C. Maddalon, Nicolas Daval, S. Loubriat, C. Bertrand-Giuliani, Walter Schwarzenbach, Bich-Yen Nguyen, G. Chabanne, M. Detard
Publikováno v:
IEEE Journal of the Electron Devices Society
Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm B
Autor:
Carlos Mazure, Bich-Yen Nguyen, Phuong Nguyen, Maud Vinet, Louis Hutin, J. Pelloux-Prayer, Christian Arvet, Nicolas Bernier, M. Casse, Claude Tabone, Oliver Faynot, S. Barraud, Jean-Michel Hartmann, Christophe Maleville, Ludovic Ecarnot
Publikováno v:
ECS Transactions. 75:59-65
We present for the first time the successful fabrication of Ω-gate P-type FETs with epitaxial compressively-strained SiGe (Ge=30%) on tensily-strained SOI substrates. The recess down to the strained-Si etch-stop layer in the source/drain (S/D) areas
Autor:
Christelle Veytizou, Christophe Figuet, Nicolas Baumel, Pascal Besson, Frédéric Mazen, Isabelle Huyet, Catherine Tempesta, Walter Schwarzenbach, Jean-Michel Hartmann, J. Widiez, Virginie Loup, Ludovic Ecarnot
Publikováno v:
ECS Transactions
Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Full
Autor:
Thierry Baron, Pascal Besson, Mickail Martin, Christophe Morales, Sebastien Sollier, Maryline Cordeau, Ionut Radu, Amelie Salaun, Thomas Signamarcheix, Ludovic Ecarnot, Marie-Christine Roure, Elodie Beche, Daniel Delprat, Christellle Veytizou, Gweltaz Gaudin, Sylvie Favier, Frank Fournel, Frédéric Mazen, Julie Widiez, Patrice Gergaud
Publikováno v:
Journal of Low Power Electronics and Applications; Volume 6; Issue 4; Pages: 19
Journal of Low Power Electronics and Applications, Vol 6, Iss 4, p 19 (2016)
Journal of Low Power Electronics and Applications, Vol 6, Iss 4, p 19 (2016)
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low tempera
Autor:
Frank Fournel, Christophe Maleville, Daniel Delprat, Ludovic Ecarnot, Sebastien Kerdiles, Yannick Le Tiec, Hubert Moriceau
Publikováno v:
Handbook of Cleaning in Semiconductor Manufacturing
Publikováno v:
Materials Science Forum. :61-74
Significant performance enhancements are offered by silicon on insulator (SOI) or strained silicon, SOI being adopted for advanced devices in sustaining Moore’s law. Sub-45 nm device options are including fully depleted (FD) devices, that are stres