Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Luckas A. Farias"'
Publikováno v:
Journal of Cryptographic Engineering. 8:271-283
This work describes a family of binary Edwards curves that admit modular reductions (an operation that can be responsible for up to 30% of the processing time in point arithmetic) twice as fast than the best usual settings, while essentially being as
Publikováno v:
2016 IEEE International Symposium on Consumer Electronics (ISCE).
This work describes a top level architecture for a general cryptographic process targeting FPGA. This architecture can be implemented for any crypto system, a symmetric or asymmetric process. The architecture allows pipeline implementation on operati
Publikováno v:
SBESC
This work describes a pipelined architecture targeting FPGA binary field multiplication. It comprises a generic real time crypto coprocessor able to operate over any field, without a specific vendor specific technology. A performance comparison of th