Zobrazeno 1 - 10
of 88
pro vyhledávání: '"Lucile Arnaud"'
Autor:
Aziliz Le Clainche, Camille Nasarre, Jing Qian, Juliette Barraux, Emma Plumey, Lucile Arnaud, Solène Cauchie, Philippe Meis
Publikováno v:
Proceedings of the SIGGRAPH Asia 2022 Computer Animation Festival.
Autor:
Lucile Arnaud, Chantal Karam, F. Servant, Severine Cheramy, S. Borel, Frank Fournel, Thierry Mourier, C. Dubarry, N. Bresson, Mathilde Gottardi, G. Mauguen, M. Assous
Publikováno v:
MRS Communications. 10:549-557
Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, ob
Autor:
Lucile Arnaud, Stephane Moreau, Joris Jourdon, Bassel Ayoub, Sandrine Lhostis, David Bouchu, Hélène Fremont
Publikováno v:
ECS Meeting Abstracts
ECS Meeting Abstracts, 2021, MA2021-02 (14), pp.662-662. ⟨10.1149/MA2021-0214662mtgabs⟩
ECS Meeting Abstracts, 2021, MA2021-02 (14), pp.662-662. ⟨10.1149/MA2021-0214662mtgabs⟩
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c1667e9ce8d036ca6cd2082ab544e31c
https://hal.archives-ouvertes.fr/hal-03467419
https://hal.archives-ouvertes.fr/hal-03467419
Autor:
Guillaume Moritz, Gael Pillonnet, Frédéric Berger, Denis Dutoit, Alexandre Arriordaz, David Coriat, Lucile Arnaud, Julian Pontes, Eric Guthmuller, Christian Bernard, Fabien Clermidy, Alexis Farcy, Didier Varreau, P. Coudrain, Alain Greiner, J. Durupt, Michel Harrand, Didier Lattard, Quentin L. Meunier, Jean Charbonnier, Ivan Miro-Panades, Sebastien Thuries, Cesar Fuguet, Arnaud Garnier, Severine Cheramy, Alain Gueugnot, Pascal Vivet, Yvain Thonnart
Publikováno v:
IEEE Journal of Solid-State Circuits
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4012e9cdfa24d7a486fffa94ba46e77
https://hal.archives-ouvertes.fr/hal-03072959/document
https://hal.archives-ouvertes.fr/hal-03072959/document
Autor:
Lucile Arnaud, David Coriat, Cesar Fuguet, Perceval Coudrain, Julian Pontes, Ivan Miro-Panades, Sebastien Thuries, J. Durupt, Didier Varreau, D. Lattard, Alexis Farcy, Alexandre Arriordaz, Eric Guthmuller, Alain Greiner, Christian Bernard, Severine Cheramy, Gael Pillonnet, Guillaume Moritz, Alain Gueugnot, Yvain Thonnart, Quentin L. Meunier, Frédéric Berger, Jean Charbonnier, Pascal Vivet, Fabien Clermidy, Michel Harrand, Arnaud Garnier, Denis Dutoit
Publikováno v:
ISSCC
In the context of high-performance computing and big-data applications, the quest for performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning the system into multiple chiplets 3D-stacked onto large-scale inte
Publikováno v:
3DIC
3D integration is a promising solution to meet the increased need for functionality, density and performance of future integrated circuits. It is an attractive technique to address the requirements of several applications such as smart imagers, high-
Autor:
V. Balan, Yann Henrion, D. Bouchu, J. Jourdon, Severine Cheramy, Stephane Moreau, L. Di Cioccio, P. Lamontagne, Frank Fournel, Lucile Arnaud, A. Jouve, Sandrine Lhostis
Publikováno v:
2019 6th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).
The paper reviews the robustness/reliability achievements and include previously published data related to the hybrid bonding module for W2W and D2W bonding techniques.
Autor:
Didier Campos, P. Coudrain, Yorrick Exbrayat, Lucile Arnaud, Stephane Minoret, F. Ponthenier, Andrea Vinci, Severine Cheramy, Alain Gueugnot, Daniel Scevola, Cesar Fuguet Tortolero, P. Chausse, Roselyne Segaud, Giovanni Romano, Christophe Aumont, Didier Lattard, Jean Charbonnier, Pierre-Emile Philip, C. Ribiere, Arnaud Garnier, Jean Michailos, Mathilde Gottardi, Raphael Eleouet, Frédéric Berger, Eric Guthmuller, Gilles Simon, Jerome Beltritti, Gilles Romero, Maxime Argoud, Denis Dutoit, Alexis Farcy, Nacima Allouti, Therry Mourier, Remi Velard, Pascal Vivet, Corinne Legalland
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interco
Autor:
Yann Henrion, Severine Cheramy, Halim Bilgen, Joris Jourdon, Alexis Farcy, Pascal Vivet, Didier Lattard, Edith Beigne, Lucile Arnaud, E. Deloffre, Imed Jani
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
Cu/oxide Hybrid Bonding (HB) technology is currently the ultimate fine pitch 3D interconnect solution to reach submicron pitches. It's an attractive technique to address the needs of several applications such as smart imagers, high-performance comput
Autor:
Thierry Lacrevaz, Jean-Charles Barbe, Remi Velard, Alexis Farcy, Lucile Cheramy, Kevin Morot, Bernard Flechet, Roselyne Segaud, Helene Jacquinot, Lucile Arnaud
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.2000-2006, ⟨10.1109/ECTC.2018.00300⟩
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.2000-2006, ⟨10.1109/ECTC.2018.00300⟩
This work aims at providing a RLCG modeling and performance optimization of Redistribution Layer (RDL) in a non-HR substrate up to 67 GHz. Similarly to TSVs, RDL modeling can not be assessed by standard parasitic extraction CAD tools. Therefore, we p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2e4971ab4228f2193472a951f2cd5b07
https://hal.science/hal-02015694
https://hal.science/hal-02015694