Zobrazeno 1 - 10
of 298
pro vyhledávání: '"Luciano Lavagno"'
Publikováno v:
IEEE Access, Vol 11, Pp 85785-85798 (2023)
High-level synthesis (HLS) is a solution for rapid prototyping of application-specific hardware using the C/C++ behavioral programming language. Designers can apply HLS directives to optimize hardware implementations by making trade-offs between cost
Externí odkaz:
https://doaj.org/article/30a9de6576bd4e74bcb9dc37b98e8170
Publikováno v:
IEEE Access, Vol 11, Pp 35830-35840 (2023)
Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as
Externí odkaz:
https://doaj.org/article/b76ef445f1e64dd4b0357248b6995dc7
Publikováno v:
IEEE Access, Vol 10, Pp 119386-119401 (2022)
The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5GNR) communication systems. Simulation effort further increases when using more real
Externí odkaz:
https://doaj.org/article/d78c293a74844718856f1fa48ba4131b
Publikováno v:
IEEE Access, Vol 10, Pp 118858-118877 (2022)
Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memo
Externí odkaz:
https://doaj.org/article/150707a356484737bc2e715d62778e70
Autor:
Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno
Publikováno v:
IEEE Access, Vol 9, Pp 54286-54297 (2021)
Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use h
Externí odkaz:
https://doaj.org/article/db168a37c1c041648add24fffb055994
Publikováno v:
IEEE Access, Vol 5, Pp 2747-2762 (2017)
FPGA-based accelerators have recently evolved as strong competitors to the traditional GPU-based accelerators in modern high-performance computing systems. They offer both high computational capabilities and considerably lower energy consumption. Hig
Externí odkaz:
https://doaj.org/article/0e2d900e43654f33b6e6c1fb7fb99c96
Publikováno v:
IEEE Access, Vol 5, Pp 8419-8432 (2017)
High-level synthesis (HLS)-based design methodologies are extremely viable for industries that are sensitive to production costs. In order to have competitive advantage, the ability to have several different implementations of the same algorithm sati
Externí odkaz:
https://doaj.org/article/0e6d17dab5404794b0e302d81efe6d8f
Publikováno v:
IEEE Access, Vol 5, Pp 18953-18974 (2017)
Using FPGA-based acceleration of high-performance computing (HPC) applications to reduce energy and power consumption is becoming an interesting option, thanks to the availability of high-level synthesis (HLS) tools that enable fast design cycles. Ho
Externí odkaz:
https://doaj.org/article/1bf3adca354043acbf8e40b89f0f15ec
Publikováno v:
IEEE Access, Vol 5, Pp 12913-12926 (2017)
Accurate tagless indoor person localization is important for several applications, such as assisted living and health monitoring. Machine learning (ML) classifiers can effectively mitigate sensor data variability and noise due to deployment-specific
Externí odkaz:
https://doaj.org/article/1885673c896f4d52b098bdc2ad6eae5a
Publikováno v:
Annals of computer science and information systems, Vol 9, Pp 141-145 (2016)
Externí odkaz:
https://doaj.org/article/921ed8a852c347c29ff00bdf5c04f583