Zobrazeno 1 - 10
of 44
pro vyhledávání: '"Lucian Shifren"'
Autor:
C. A. Paz de Araujo, Jolanta Celinska, Chris R. McWilliams, Lucian Shifren, Greg Yeric, X. M. Henry Huang, Saurabh Vinayak Suryavanshi, Glen Rosendale, Valeri Afanas’ev, Eduardo C. Marino, Dushyant Madhav Narayan, Daniel S. Dessau
Publikováno v:
APL Materials, Vol 10, Iss 4, Pp 040904-040904-12 (2022)
Transition metal oxides (TMOs) and post-TMOs (PTMOs), when doped with carbon, show non-volatile current–voltage characteristics, which are both universal and repeatable. We have shown spectroscopic evidence of the introduction of carbon-based impur
Externí odkaz:
https://doaj.org/article/88c3b8f50683492bac6303c9b42ff659
Autor:
Saurabh V. Suryavanshi, Greg Yeric, Max Irby, X. M. Henry Huang, Glen Rosendale, Lucian Shifren
Publikováno v:
2022 IEEE International Memory Workshop (IMW).
Autor:
Dennis Sylvester, Supreet Jeloka, Ronald G. Dreslinski, Trevor Mudge, Saurabh Sinha, David Blaauw, Nathaniel Pinckney, Brian Cline, Lucian Shifren
Publikováno v:
IEEE Design & Test. 34:31-38
Near-threshold operations provide a powerful knob for improving energy efficiency and alleviating on-chip power densities. This article explores the impact of newest FinFET CMOS technologies (from 40 to 7 nm) on near-threshold computing in terms of p
Autor:
Vikas Chandra, Greg Yeric, David Victor Pietromonaco, Brian Cline, Saurabh Sinha, Shidhartha Das, Robert Campbell Aitken, Lucian Shifren
Publikováno v:
IET Computers & Digital Techniques. 10:315-322
Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it ac
Autor:
Lawrence T. Clark, Vinay Vashishtha, Aditya Gujja, Chandarasekaran Ramamurthy, Saurabh Sinha, Greg Yeric, Brian Cline, Lucian Shifren
Publikováno v:
Microelectronics Journal. 53:105-115
We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific f
Autor:
Craig Riddet, Binjie Cheng, Greg Yeric, Xingsheng Wang, Asen Asenov, Saurahb Sinha, Robert Campbell Aitken, Salvatore Maria Amoroso, Lucian Shifren, Fikru Adamu-Lema
Publikováno v:
IEEE Transactions on Electron Devices. 61:3372-3378
In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping lev
Autor:
Andrew R. Brown, Craig Riddet, Saurabh Sinha, Binjie Cheng, Robert Campbell Aitken, Brian Cline, Craig Alexander, Lucian Shifren, Greg Yeric, Asen Asenov, Vikas Chandra, Campbell Millar
Publikováno v:
IEEE Transactions on Electron Devices. 61:2271-2277
In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constan
Autor:
Lucian Shifren, Dennis Sylvester, Nathaniel Pinckney, David Blaauw, Ronald G. Dreslinski, Brian Cline, Trevor Mudge, Saurabh Sinha, Supreet Jeloka
Publikováno v:
DAC
In recent years, operating at near-threshold supply voltages has been proposed to improve energy efficiency in circuits, yet decreased efficacy of dynamic voltage scaling has been observed in recent planar technologies. However, foundries have introd
Autor:
Robert Campbell Aitken, Y. Wang, Lucian Shifren, Andrew R. Brown, Salvatore Maria Amoroso, Greg Yeric, Xingsheng Wang, Ewan Towie, Craig Riddet, Jinfeng Kang, Talib Al-Ameri, Xiaoyan Liu, Asen Asenov, Binjie Cheng, Saurabh Sinha, Vihar P. Georgiev, David Reid
In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8121893761e03623c9fb488581f5b17c
https://eprints.gla.ac.uk/110788/2/110788.pdf
https://eprints.gla.ac.uk/110788/2/110788.pdf
Autor:
Cory E. Weber, Martin D. Giles, M. Stettler, Roza Kotlyar, Lucian Shifren, Thomas D. Linton, S. Cea
Publikováno v:
Journal of Computational Electronics. 8:110-123
We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo met