Zobrazeno 1 - 10 of 36 pro vyhledávání: '"Lucas A. Tambara"'
1
Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects
Autor: Luis A. C. Benites, Nemitala Added, Fabio Benevenuti, Nilberto H. Medina, Adria Barros de Oliveira, Marcilei A. G. Silveira, Fernanda Lima Kastensmidt, Lucas A. Tambara, V. A. P. Aguiar
Publikováno v: Repositório Institucional da USP (Biblioteca Digital da Produção Intelectual)
Universidade de São Paulo (USP)
instacron:USP
This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mi
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::648897fe7a0ec74ceffedf45830b1fad
https://doi.org/10.1109/tns.2020.2995729
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2
Reliability–Performance Analysis of Hardware and Software Co-Designs in SRAM-Based APSoCs
Autor: Marcilei A. G. Silveira, Paolo Rech, Nemitala Added, Lucas A. Tambara, Nilberto H. Medina, Filipe M. Lins, V. A. P. Aguiar, Fernanda Lima Kastensmidt
Publikováno v: Repositório Institucional da USP (Biblioteca Digital da Produção Intelectual)
Universidade de São Paulo (USP)
instacron:USP
All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b0693baecdafdae094c0bfca7bd4d68a
https://doi.org/10.1109/tns.2018.2844250
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3
On the Reliability of Linear Regression and Pattern Recognition Feedforward Artificial Neural Networks in FPGAs
Autor: F. Libano, Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Jorge Tonfat
Publikováno v: IEEE Transactions on Nuclear Science. 65:288-295
In this paper, we experimentally and analytically evaluate the reliability of two state-of-the-art neural networks for linear regression and pattern recognition (multilayer perceptron and single-layer perceptron) implemented in a system-on-chip compo
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b73c32950e2bed780719e842b7ec9343
https://doi.org/10.1109/tns.2017.2784367
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4
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment
Autor: Salvatore Danzeca, Markus Brugger, Eduardo Chielle, Lucas A. Tambara, A. Masi, Fernanda Lima Kastensmidt, Georgios Tsiligiannis
Publikováno v: Microelectronics Reliability. :640-643
All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall programmable flexibility and system performance at lower costs. Such characteristics make APSoCs very suitable and attractive for critical environments, such as th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::07d4096b3f69afb833a47dca0b6c16a9
https://doi.org/10.1016/j.microrel.2017.06.049
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5
Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs
Autor: André Santos, Fernanda Lima Kastensmidt, Jorge Tonfat, Lucas A. Tambara
Publikováno v: Microprocessors and Microsystems. 51:209-219
SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore d
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7baf0cd53d19226cdc3942964ec3e838
https://doi.org/10.1016/j.micpro.2017.04.016
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6
Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors
Autor: Jorge Tonfat, Fernanda Lima Kastensmidt, Marcilei A. G. Silveira, Vitor A. P. Aguiar, Lucas A. Tambara, Nemitala Added, Fernando Aguirre, André Santos, Nilberto H. Medina
Publikováno v: IEEE Transactions on Nuclear Science. 64:874-881
The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HL
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::83bd000965db1865a9fc6fc599b24fcd
https://doi.org/10.1109/tns.2017.2648978
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8
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission
Autor: Jorge Tonfat, Eduardo Chielle, Fabio Benevenuti, Carlos Alberto Zaffari, Otavio Durao, Fernanda Lima Kastensmidt, Lucas A. Tambara, João Baptista dos Santos Martins
Publikováno v: IPDPS Workshops
The use of reconfigurable devices, such as FPGAs, in nanosatellites allows the prototyping and evaluation in flight of different categories of designs of interest to the aerospace technology. It includes blending of experimental or well-proven legacy
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::558a87c9331de0b8c460a288246540c5
https://doi.org/10.1109/ipdpsw.2019.00032
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9
Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs
Autor: Jorge Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Eduardo Chielle, Paolo Rech
Publikováno v: IEEE Transactions on Nuclear Science. 63:2217-2224
All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are pr
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f0f2a8cfaf8180dc6c75e1ffde0ce4ed
https://doi.org/10.1109/tns.2016.2522508
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10
Dynamic Heavy Ion SEE Testing of Microsemi RTG4 Flash-based FPGA Embedding a LEON4FT-based SoC
Autor: Javier Jalle, Lucas A. Tambara, Richard Sharp, Fredrik Sturesson, Jan Andersson
Publikováno v: 2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS).
The Cobham Gaisler LEON4FT is a fault-tolerant synthesizable VHDL model of a 32-bit processor core, compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for System-on-Chip (SoC) designs. The processor i
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4523e528c67096cda793e30c5e4acb13
https://doi.org/10.1109/radecs45761.2018.9328725
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