Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Luca Mattii"'
Autor:
P. Schuddinck, Max M. Shulaker, Romain Ritzenthaler, Alessio Spessot, Dimitrios Rodopoulos, Chi-Shuen Lee, Praveen Raghavan, Aaron Thean, Peter Debacker, Luca Mattii, Francky Catthoor, Syed Muhammed Yasser Sherazi, Marie Garcia Bardon, D. Yakimets, Rogier Baert, Gage Hills, Subhasish Mitra, H.-S. Philip Wong, Doyoung Jang, Gerben Doornbos, Iuliana Radu
Publikováno v:
IEEE Transactions on Nanotechnology. 17:1259-1269
© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a0c3d32c29c32be8a49eb7552ab3243f
https://doi.org/10.1109/tnano.2018.2871841
https://doi.org/10.1109/tnano.2018.2871841
Autor:
P. Schuddinck, Bertrand Parvais, M. Garcia Bardon, Diederik Verkest, Yasser Sherazi, Hans Mertens, Rogier Baert, D. Yakimets, Luca Mattii, Anda Mocuta, Doyoung Jang
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d0ad6054546d7388462df3c56204cf70
https://doi.org/10.1109/vlsit.2018.8510633
https://doi.org/10.1109/vlsit.2018.8510633
Autor:
Alessio Spessot, Bharani Chava, J. Ryckaert, Peter Debacker, Luca Mattii, Diederik Verkest, Syed Muhammad Yasser Sherazi
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XII.
Standard cell track height scaling has been identified as an option to provide significant area savings. A direct consequence of track height reduction is that the width of the power rails needs to be reduced to accommodate patterning constraints as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e48ce5301963b4e807d1da7a0560d21
https://doi.org/10.1117/12.2293500
https://doi.org/10.1117/12.2293500
Autor:
Luca Mattii, Drago Mir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan
Publikováno v:
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2282209182d7159bab4ca382d0324b04
https://doi.org/10.1109/iccad.2017.8203764
https://doi.org/10.1109/iccad.2017.8203764
Autor:
Philippe Hurat, Ya-Chieh Lai, Ryoung-han Kim, Jun Ye, Cyrus E. Tabery, Yi Zou, Vincent Arnoux, Michel Luc Cote, Luca Mattii, Praveen Raghavan
Publikováno v:
Optical Microlithography XXX.
Publisher’s Note: This paper, originally published on 30-March, 2017, was replaced with a corrected/revised version on 6-April, 2017. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Cust
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b46e3b9a60719e1f369be560a2ada850
https://doi.org/10.1117/12.2263861
https://doi.org/10.1117/12.2263861
Autor:
Bharani Chava, P. Schuddinck, Luca Mattii, Dimitrios Rodopoulos, Peter Debacker, Rogier Baert, Mladen Berekovic, Marie Garcia Bardon, Julien Ryckaert, Syed Muhammad Yasser Sherazi, Dragomir Milojevic, Vassilios Gerousis, Praveen Raghavan
Publikováno v:
Journal of Micro/Nanolithography, MEMS, and MOEMS. 17:1
Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the rou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e5a39a0a682e6121fae6752ac94e2ba
https://doi.org/10.1117/1.jmm.17.1.013503
https://doi.org/10.1117/1.jmm.17.1.013503