Zobrazeno 1 - 10
of 73
pro vyhledávání: '"Luca Amaru"'
Autor:
Eleonora Testa, Luca Amaru, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Publikováno v:
IEEE Access, Vol 8, Pp 226828-226844 (2020)
In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional prop
Externí odkaz:
https://doaj.org/article/cc668a7109f1414c9d4538abe9cb099b
Autor:
Eric Mlinar, Stephen Whiteley, Anton Belov, Song Chen, Luca Amaru, Tong Liu, Yalan Zhang, Taufik Arifin, Min Pan, Troy Barbee, Rajinder Singh, Amir Ajami, Danny Rawlings, Giulia Meuli, Rajesh Kumar, Arturo Salz, Scott Chase, Jamil Kawa
Publikováno v:
IEEE Transactions on Applied Superconductivity. 33:1-7
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1becd1f32aea32ae2240074f32b29c99
https://doi.org/10.1109/tasc.2023.3238298
https://doi.org/10.1109/tasc.2023.3238298
Autor:
Giulia Meuli, Vinicius Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca Amaru, Scott Chase, Jamil Kawa, Giovanni De Micheli
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).
Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconductin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::73a6e1a43a10bbf56fca6cbe736787bb
https://doi.org/10.23919/date54114.2022.9774558
https://doi.org/10.23919/date54114.2022.9774558
Autor:
Felipe S. Marranghello, Luca Amaru, Jiong Luo, Patrick Vuillod, Vinicius N. Possani, Alan Mishchenko, Giovanni De Micheli, Eleonora Testa, Christopher Casares
Publikováno v:
DAC
Look-up Table (LUT) mapping and optimization is an important step in Field Programmable Gate Arrays (FPGAs) design. The effectiveness of LUT synthesis improved dramatically in the last decades, thanks to optimization and mapping innovations naturally
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d762f30863a7e9e29a7b2f2d8a42a7b0
https://doi.org/10.1109/dac18074.2021.9586132
https://doi.org/10.1109/dac18074.2021.9586132
Publikováno v:
DAC
The paper addresses a key aspect of efficient computation in logic synthesis and formal verification, namely, the integration of a circuit simulator and a Boolean satisfiability solver. A novel way of interfacing these is proposed along with a fast p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6bce593b9ec8643a6add35b53df7bb2
https://doi.org/10.1109/dac18074.2021.9586331
https://doi.org/10.1109/dac18074.2021.9586331
Autor:
Cunxi Yu, Matheus T. Moreira, Pierre-Emmanuel Gaillardon, Yingjie Li, Luca Amaru, Walter Lau Neto
Publikováno v:
DAC
Recently we have seen many works that leverage Machine Learning (ML) techniques in optimizing Electronic Design Automation (EDA) process. However, the uses of ML techniques are limited to learning forecasting models of existing EDA algorithms, instea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ecaaceaffd791a6ba429558c6fb3057
https://doi.org/10.1109/dac18074.2021.9586230
https://doi.org/10.1109/dac18074.2021.9586230
Publikováno v:
ASP-DAC
To tackle the involved complexity, Electronic Design Automation (EDA) tools are broken in well-defined steps, each operating at different abstraction levels. Higher levels of abstraction shorten the flow run-time while sacrificing correlation with th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27cde1b3e6361feaa0106419fa0b1960
https://doi.org/10.1145/3394885.3431560
https://doi.org/10.1145/3394885.3431560
Autor:
Eleonora Testa, Christopher Casares, Jiong Luo, Patrick Vuillod, Felipe S. Marranghello, Vinicius N. Possani, Luca Amaru, Alan Mishchenko, Giovanni De Micheli
Publikováno v:
DAC
SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c84e8013bf3fb4759653720963f7de6a
https://doi.org/10.1109/dac18072.2020.9218691
https://doi.org/10.1109/dac18072.2020.9218691
Publikováno v:
DATE
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found appl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d20f6478fd0cb89e8ff7d5a0b9f5f372
https://doi.org/10.23919/date48585.2020.9116467
https://doi.org/10.23919/date48585.2020.9116467
Autor:
Xifan Tang, Luca Amaru, Max Austin, Pierre-Emmanuel Gaillardon, Scott Temple, Walter Lau Neto
Publikováno v:
DATE
We present a new logic synthesis framework which produces efficient post-technology mapped results on heterogeneous networks containing a mix of different types of logic. This framework accomplishes this by breaking down the circuit into sections usi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7862db274ec266c103333705318c97ea
https://doi.org/10.23919/date48585.2020.9116534
https://doi.org/10.23919/date48585.2020.9116534