Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGA

Autor: Cherif, Zouha, Danger, Jean-Luc, Lozac'H, Florent, Mathieu, Yves, Bossuet, Lilian

Publikováno v: Proceedings of International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013
International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013
International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4

International audience; This paper presents a comparative study of delay Physically Unclonable Functions (PUFs) designed in CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). The performances are analyzed for two types of silicon PUFs,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::08f25873a913c532592a06a3d199fcde
https://hal.archives-ouvertes.fr/hal-00859079

Physically Unclonable Function: Principle, Design and Characterization of the Loop PUF.

Autor: Cherif, Zouha, Danger, Jean-Luc, Lozac'h, Florent, Nguyen, Philippe

Publikováno v: Trusted Computing for Embedded Systems; 2015, p115-133, 19p