Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Louis N. Hutter"'
Publikováno v:
2007 IEEE International Conference on Microelectronic Test Structures.
Capacitor matching is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. As technologies advance, however, new challenges emer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38821e97077fb729757ed82536a32954
https://doi.org/10.1109/icmts.2007.374467
https://doi.org/10.1109/icmts.2007.374467
Publikováno v:
[Proceedings] APEC '92 Seventh Annual Applied Power Electronics Conference and Exposition.
A 2.0 mu m BiCMOS process incorporating 30 V bipolar, 5-50 V CMOS, precision analog elements, and 45 V power DMOS transistors with 2.0 m Omega cm/sup 2/ R/sub DSON/ area is presented. The process is compatible with a mature mixed-signal application-s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62a8857ca6c3765a6ce9b612a1e1f9c1
https://doi.org/10.1109/apec.1992.228366
https://doi.org/10.1109/apec.1992.228366
Autor:
Chin-Yu Tsai, J.-Y. Yang, Taylor R. Efland, Jozef C. Mitros, J. Arch, Louis N. Hutter, H.-T. Yuan, John P. Erdeljac
Publikováno v:
International Electron Devices Meeting. Technical Digest.
The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40a51950177e7856904c0675e0f3c7c1
https://doi.org/10.1109/iedm.1996.553628
https://doi.org/10.1109/iedm.1996.553628
Autor:
Jozef C. Mitros, A. Tessmer, John P. Erdeljac, Taylor R. Efland, L.X. Springer, Jeffrey P. Smith, Chin-Yu Tsai, Sameer Pendharkar, P. Madhani, Louis N. Hutter
Publikováno v:
Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting.
A 0.7 /spl mu/m BiCMOS technology is described. The baseline process offers digital and analog CMOS, a variety of bipolar devices, poly resistors, poly-poly capacitors, Schottky diodes, noise isolation, and 3 levels of metal. Power DMOS transistors w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f308d1bc6543557158a151576de7fec
https://doi.org/10.1109/bipol.1997.647424
https://doi.org/10.1109/bipol.1997.647424
Autor:
Jeffrey P. Smith, John P. Erdeljac, Taylor R. Efland, Louis N. Hutter, Sameer Pendharkar, Jozef C. Mitros, A. Tessmer, C.-Y. Tsai
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55e1e6e6efbab1f7b030a67e7e70ce06
https://doi.org/10.1109/iedm.1997.650401
https://doi.org/10.1109/iedm.1997.650401
Publikováno v:
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting.
The design aspects of a 9-channel ultra-SCSI transceiver chip are discussed including improvements to speed, power consumption and die size over a previous generation chip, Discussion of the enabling linear BiCMOS technology and an ESD strategy, crit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63f004c8ce982533c95cd10f320918df
https://doi.org/10.1109/bipol.1995.493886
https://doi.org/10.1109/bipol.1995.493886
Autor:
Louis N. Hutter, Walter Bucksch, Konrad Wagensohner, Erich Bayer, Kevin Scoones, John P. Erdeljac
Publikováno v:
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting.
A 1.0 micron BiCMOS process, with lateral DMOS as an available process extension, is presented for mixed-signal and power applications, providing a broad range of active and passive components. The DMOS transistor offers 45-60 V capability with Rsp=1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::982b130c7910879c80eed20cc2e3bc8e
https://doi.org/10.1109/bipol.1995.493883
https://doi.org/10.1109/bipol.1995.493883
Autor:
M. Nair, R. Jumpertz, B. El Kareh, A. Bellaour, Louis N. Hutter, M. Mercer, T. Scharnagl, L. Stroth, L. Hodgson, J. Seitchik, S. Dunn, M. Jaumann, B. Benna, G. Hoffleisch, M. Thompson, M. Schiekofer, F.S. Johnson, S. John, U. Schulz, K. Violette, B. Williams, J. Erdeljac, B. Staufer, J. Ai, C. Shen, K. Schimpf, K. Benaissa, D. Tatman
Publikováno v:
Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212).
A new SiGe integration technique is introduced that allows the low cost integration of a self-aligned 65 GHz SiGe heterojunction bipolar transistor (HBT) with a 0.55dB noise figure (NF) using simple processing steps and a non-selective SiGe epitaxy d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e5182b1943fea1d278f85a87877ccb5a
https://doi.org/10.1109/bipol.2001.957856
https://doi.org/10.1109/bipol.2001.957856
Autor:
E. Mindricelu, T. Debolske, Jeffrey P. Smith, D. Hannaman, M. McNutt, J.C. Brito, R. Higgins, Taylor R. Efland, R.V. Taylor, P. Fleischmann, Louis N. Hutter, Sameer Pendharkar, W. Nehrer
Publikováno v:
Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212).
A 30 V, 0.5 /spl mu/m, triple level metal (TLM) + thick top copper metal, power-BiCMOS technology for Hard Disk Drive (HDD) servo applications is described. Based on a die area analysis, a vital few components and process features were optimized over
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6657ca03e9af97d199fa58f2c02db5be
https://doi.org/10.1109/bipol.2001.957888
https://doi.org/10.1109/bipol.2001.957888
Autor:
I. Nishimura, C.M. Thee, D. Abbott, Louis N. Hutter, C. Hoffart, V. Arellano, Taylor R. Efland, W. Chang, C.C. Shen, Q. Mai, Sameer Pendharkar, H. Vanhorn, M. Pierce, M. Buschbom, C. Williams
Publikováno v:
Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).
A metal system consisting of thick electroplated copper leads having a top plating of nickel and palladium cap are integrated on top of power ICs to form a bondable LeadFrameOnChip surface.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fad9d822ec2fb6db4af73a0e7a8440d
https://doi.org/10.1109/ispsd.2001.934560
https://doi.org/10.1109/ispsd.2001.934560