Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Lorenzo Pieralisi"'
Autor:
Miltos D. Grammatikakis, Giuseppe Maruccia, Marcello Coppola, Riccardo Locatelli, Lorenzo Pieralisi
Publikováno v:
Design of Cost-Efficient Interconnect Processing Units ISBN: 9781420044713
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9a4ba80496471a5392230779caff4774
https://doi.org/10.1201/9781315219936-1
https://doi.org/10.1201/9781315219936-1
Autor:
Michael Hübner, Tommaso DeMarco, Florian Ries, Antonio Marcello Coppola, Jürgen Becker, Matthias Kühnle, Riccardo Locatelli, Claudio Mucci, Giuseppe Maruccia, Fabio Campi, A. Deledda, Lorenzo Pieralisi
Publikováno v:
IEEE Design & Test of Computers. 25:442-451
Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1d1c7b65f685ba2b72b4a6207f20daf
https://doi.org/10.1109/mdt.2008.150
https://doi.org/10.1109/mdt.2008.150
Autor:
Riccardo Locatelli, Giuseppe Maruccia, Miltos D. Grammatikakis, Marcello Coppola, Lorenzo Pieralisi
Publikováno v:
Design of Cost-Efficient Interconnect Processing Units ISBN: 9781420044713
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b3188fcc1c68b56ec2847749f5130e93
https://doi.org/10.1201/9781420044720.ch4
https://doi.org/10.1201/9781420044720.ch4
Autor:
Giuseppe Maruccia, Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Lorenzo Pieralisi
Publikováno v:
Design of Cost-Efficient Interconnect Processing Units ISBN: 9781420044713
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8ee81849800c9bd4e13e6671357b7d02
https://doi.org/10.1201/9781420044720.ch5
https://doi.org/10.1201/9781420044720.ch5
Autor:
Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Miltos D. Grammatikakis, Marcello Coppola
Publikováno v:
System-on-Chip Design and Technologies ISBN: 9781420044713
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c0a140cf3c7dab7c9ed425ab291bcfd3
https://doi.org/10.1201/9781420044720
https://doi.org/10.1201/9781420044720
Autor:
Lorenzo Pieralisi, Miltos D. Grammatikakis, Riccardo Locatelli, Marcello Coppola, Giuseppe Maruccia
Publikováno v:
Design of Cost-Efficient Interconnect Processing Units ISBN: 9781420044713
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dff77e879ab5f86638c767f5a65b98e8
https://doi.org/10.1201/9781420044720.ch2
https://doi.org/10.1201/9781420044720.ch2
Autor:
Arseni Vitkovski, Lorenzo Pieralisi, Tommaso DeMarco, Fabio Campi, Giuseppe Maruccia, Claudio Mucci, F. Ries, Michael Huebner, Riccardo Locatelli, Philippe Millet, M. Kuehnle, A. Deledda, Philippe Bonnot, Marcello Coppola, Jürgen Becker, Arnaud Grasset
Publikováno v:
DATE
Reconfigurable architectures and NoC (Network-on- Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of resear
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5983f6d3001164789ad0a7fdacd9cc7
https://doi.org/10.1145/1403375.1403700
https://doi.org/10.1145/1403375.1403700
Publikováno v:
SoC
Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4140d2903fd2c8f1db10bde568691bf0
https://doi.org/10.1109/issoc.2004.1411133
https://doi.org/10.1109/issoc.2004.1411133