Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Lorenzo Chelini"'
Autor:
Adam Siemieniuk, Lorenzo Chelini, Andi Drebes, Henk Corporaal, Martin Kong, Asif Ali Khan, Tobias Grosser, Jeronimo Castrillon
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:1674-1686
Memristive devices promise an alternative approach toward non-Von Neumann architectures, where specific computational tasks are performed within the memory devices. In the Machine Learning (ML) domain, crossbar arrays of resistive devices have shown
Publikováno v:
ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2019, 16 (4), pp.4:1-25. ⟨10.1145/3372266⟩
ACM Transactions on Architecture and Code Optimization, 2019, 16 (4), pp.4:1-25. ⟨10.1145/3372266⟩
ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2019, 16 (4), pp.4:1-25. ⟨10.1145/3372266⟩
ACM Transactions on Architecture and Code Optimization, 2019, 16 (4), pp.4:1-25. ⟨10.1145/3372266⟩
Increasingly complex hardware makes the design of effective compilers difficult. To reduce this problem, we introduce Declarative Loop Tactics , which is a novel framework of composable program transformations based on an internal tree-like program r
Autor:
Henk Corporaal, Albert Cohen, Nicolas Vasilache, Lorenzo Chelini, Tobias Grosser, Oleksandr Zinenko, Andi Drebes
Publikováno v:
CGO 2021 : International Symposium on Code Generation and Optimization
CGO 2021 : International Symposium on Code Generation and Optimization, Feb 2021, Seoul / Virtual, South Korea
CGO
CGO 2021 : International Symposium on Code Generation and Optimization, Feb 2021, Seoul / Virtual, South Korea
CGO
International audience; Multi-level intermediate representations (IR) show great promise for lowering the design costs for domain-specific compilers by providing a reusable, extensible, and non-opinionated framework for expressing domain-specific and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::795d5bb4bf4ddca92237b0b721acca01
https://hal.inria.fr/hal-03139764
https://hal.inria.fr/hal-03139764
Publikováno v:
SCOPES
Despite years of research, the optimization strategy of loop-level optimization frameworks remains fragile when addressing modern and heterogeneous architectures. Furthermore, optimizers act as an opaque operation, a black-box, to the users, forcing
Publikováno v:
PACT
We present Polygeist, a new compilation flow that connects the MLIR compiler infrastructure to cutting edge polyhedral optimization tools. It consists of a C and C++ frontend capable of converting a broad range of existing codes into MLIR suitable fo
Publikováno v:
PACT
PACT '20: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques
PACT '20: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques
To this day, polyhedral optimizing compilers use either extremely rigid (but accurate) cost models, one-size-fits-all general-purpose heuristics, or auto-tuning strategies to traverse and evaluate large optimization spaces. In this paper, we introduc
Autor:
Henk Corporaal, Sander Stuijk, Lorenzo Chelini, Stefano Corda, Gagandeep Singh, Roel Jordans, Ahsan Javed Awan, Albert-Jan Boonstra
Publikováno v:
Microprocessors and Microsystems
Microprocessors and Microsystems, 71:102868. Elsevier
Microprocessors and Microsystems, 71:102868. Elsevier
The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integratio
Autor:
Lorenzo Chelini, Jan van Lunteren, Ronald P. Luijten, Stefano Corda, Florian Auernhammer, Christoph Hagleitner, Dionysios Diamantopoulos, Gagandeep Singh
Publikováno v:
DATE
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Application and technology trends are increasingly forcing computer systems to be designed for specific workloads and application domains. Although memory is one of the key components impacting the performance and power consumption of state-of-art co
Publikováno v:
HAL
[Research Report] RR-9243, Inria; ENS Paris-Ecole Normale Supérieure de Paris; ETH Zurich; TU Delft; IBM Zürich. 2018
[Research Report] RR-9243, Inria; ENS Paris-Ecole Normale Supérieure de Paris; ETH Zurich; TU Delft; IBM Zürich. 2018
Despite the availability of sophisticated automatic optimizers, performance-critical code sections are in practice still tuned by human experts. Pragma-based languages such as OpenMP or OpenACC are the standard interface to apply such transformations
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::92c88337f07ed3f38cf00ba8b288d77c
https://hal.inria.fr/hal-01965599
https://hal.inria.fr/hal-01965599